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Journal ArticleDOI

Automated analysis of concurrent systems with the constrained expression toolset

TLDR
In this article, the authors present a toolset for automating the main constrained expression analysis techniques and the results of experiments with that toolset are reported. The toolset is capable of carrying out completely automated analyses of a variety of concurrent systems, starting from source code in an Ada-like design language and producing system traces displaying the properties represented by the analysts queries.
Abstract
The constrained expression approach to analysis of concurrent software systems can be used with a variety of design and programming languages and does not require a complete enumeration of the set of reachable states of the concurrent system. The construction of a toolset automating the main constrained expression analysis techniques and the results of experiments with that toolset are reported. The toolset is capable of carrying out completely automated analyses of a variety of concurrent systems, starting from source code in an Ada-like design language and producing system traces displaying the properties represented bv the analysts queries. The strengths and weaknesses of the toolset and the approach are assessed on both theoretical and empirical grounds. >

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Citations
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Proceedings ArticleDOI

Patterns in property specifications for finite-state verification

TL;DR: A survey of available specifications found that most are instances of the proposed pattern-based approach to the presentation, codification and reuse of property specifications for finite-state verification.
Journal ArticleDOI

Discovering models of software processes from event-based data

TL;DR: In this article, the authors describe a Markov method for process discovery, as well as two additional methods that are adopted from other domains and augmented for their purposes, and compare the methods and discuss their application in an industrial case study.
Proceedings ArticleDOI

Property specification patterns for finite-state verification

TL;DR: This work proposes a pattern-based approach to the presentation, codification and reuse of property specifications for finite-state verification, believing that a primary cause rests with the fact that practitioners are unfamiliar with specification processes, notations, and strategies.
PatentDOI

Concurrent engineering design tool and method

TL;DR: A computer-based engineering design system to design a part, a tool to make the part, and the process to making the part by accessing the plurality of feature templates in the memory to locate one or more primitive objects that perform the oneor more predetermined functions.

Software Process Validation: Quantitatively Measuring the Correspondence of a Process to a Model ; CU-CS-840-97

TL;DR: Process validation takes a process execution and a process model, and measures the level of correspondence between the two, which provides detailed information once a high-level measurement indicates the presence of a problem.
References
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Journal ArticleDOI

Automatic verification of finite-state concurrent systems using temporal logic specifications

TL;DR: It is argued that this technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finite-state concurrent systems.
Journal ArticleDOI

A new solution of Dijkstra's concurrent programming problem

TL;DR: A simple solution to the mutual exclusion problem is presented which allows the system to continue to operate despite the failure of any individual component.
Journal ArticleDOI

An optimal algorithm for mutual exclusion in computer networks

TL;DR: An algorithm is proposed that creates mutual exclusion in a computer network whose nodes communicate only by messages and do not share memory, and it is shown that the number can be contained in a fixed amount of memory by storing it as the residue of a modulus.
Journal ArticleDOI

A Stubborn Attack On State Explosion

Antti Valmari
TL;DR: The LTL-preserving stubborn set method is presented for reducing the amount of work needed in the automatic verification of concurrent systems with respect to linear-time temporal logic specifications.