Avoidance of hot electron operation of voltage stressed bootstrap drivers

TLDR: In this article, an improved field effect transistor circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers is described. But the circuit is not suitable for high switching speed applications.

Abstract: An improved field effect transistor circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a simultaneous gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range. The voltage control means is adapted to reduce FET drain to source voltage by connecting a plurality of FET devices in series to reduce the drain to source voltage drop across each device. The drain to source voltage is further defined by connecting the common nodes of successive series connected devices to a specified voltage source that is less than a characteristic hot electron drain to source voltage. The voltage control means also includes a gate voltage clamping FET that is adapted to hold down the gate of a device when the drain to source voltage of the device rises above a particular hot electron voltage. The voltage control means further comprises a plurality of timing pulses that define particular combinations of gate and drain to source device voltages that are less than characteristic combined hot electron voltages. The voltage control means further includes devices with width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages to maintain a minimum drain to source voltage drop. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.