Patent
Balun transformer with improved harmonic suppression
TLDR
In this article, the reaction circuit component is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency, which is the same as in this paper.Abstract:
An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.read more
Citations
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Patent
Semiconductor Device and Method of Forming RF Balun Having Reduced Capacitive Coupling and High CMRR
Robert C. Frye,Kai Liu +1 more
TL;DR: In this paper, a first capacitor is coupled between the first and second ends of the first conductive trace, and a second capacitor is wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupling to a second terminal of a second node.
Patent
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TL;DR: In this paper, a thin film balun that can be made smaller and thinner while maintaining required balun characteristics is provided, which includes an unbalanced transmission line UL, a balanced transmission line BL, and a ground terminal G connected to the second coil portion C 2 via a C component D.
Patent
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Patent
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TL;DR: A balanced-unbalanced (balun) signal transformer as mentioned in this paper includes an unbalanced port, a balanced port coupled to the unbalanced one, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to first terminal, and a first inductor coupled to ground and the first capacitor, a second capacitor coupled with the second terminal.
Patent
Semiconductor device and operating method thereof
TL;DR: In this article, the authors describe a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory devices, and process the request on a second memory device instead of the original memory device when the multi-bits error has been occurred.
References
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Patent
Multi-layer radio frequency transformer
TL;DR: In this paper, a transformer (300) includes several layers of substrate (202, 204, 206, 208), sandwiched between the second set of layers (204 and 206) is a runner that forms two other interconnected spirals (321 and 322) forming two half coils of the transformer secondary.
Patent
Compact multilayer BALUN for RF integrated circuits
TL;DR: In this article, the authors propose to stack at least one of the primary or secondary layers in a multi-layer arrangement of a compact BALUN transformer, which provides an increase of impedance for impedance matching purposes.
Patent
Method of manufacturing an on-chip transformer balun
TL;DR: In this article, a method of manufacturing an on-chip transformer balun includes creating, on a semiconductor substrate, a primary winding having at least one substantially symmetrical primary turn on a first dielectric layer and at least 1 metal bridge on a second layer.
Patent
Apparatus and method for implementing a low-noise amplifier and mixer
TL;DR: In this article, the authors present an apparatus for modifying a radio frequency signal, which includes a mixer, an amplifier module and an interface circuit, and the interface circuit is interposed between the mixer and the amplifier module, so that a DC bias current flows from the first amplifier stage through the interface module into the second amplifier stage.
Patent
Integrated high frequency balanced-to-unbalanced transformers
TL;DR: In this paper, the layout of the primary and secondary inductors for the minimization of capacitive effects between layers while using a minimal number of metal layers is discussed, and two solutions are provided, one having a symmetrical primary inductor in a 4-metal layer implementation and another having a non-symmetrical primary induction in a 3-metal level implementation.