Book ChapterDOI
Checking Safety Properties Using Induction and a SAT-Solver
Mary Sheeran,Satnam Singh,Gunnar Stålmarck +2 more
- pp 108-125
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TLDR
Some novel induction-based methods are described, and it is shown how they are related to more standard fixpoint algorithms for invariance checking and preliminary experimental results in the verification of FPGA cores are presented.Abstract:
We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-solver. We describe some novel induction-based methods, and show how they are related to more standard fixpoint algorithms for invariance checking. We also present preliminary experimental results in the verification of FPGA cores. This demonstrates the practicality of combining a SAT-solver with induction for safety property checking of hardware in a real design flow.read more
Citations
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Model checking
TL;DR: Model checking tools, created by both academic and industrial teams, have resulted in an entirely novel approach to verification and test case generation that often enables engineers in the electronics industry to design complex systems with considerable assurance regarding the correctness of their initial designs.
Book ChapterDOI
Bounded Model Checking
TL;DR: This article surveys a technique called Bounded Model Checking (BMC), which uses a propositional SAT solver rather than BDD manipulation techniques, and is widely perceived as a complementary technique to BDD-based model checking.
Book ChapterDOI
Satisfiability Modulo Theories
Clark Barrett,Cesare Tinelli +1 more
TL;DR: The architecture of a lazy SMT solver is discussed, examples of theory solvers are given, how to combine such solvers modularly is shown, and several extensions of the lazy approach are mentioned.
Book ChapterDOI
Interpolation and SAT-Based Model Checking
TL;DR: In this article, a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants was proposed, which is greatly more efficient than BDD-based symbolic model-checking.
Journal Article
Interpolation and SAT-based model checking
TL;DR: In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.
References
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Model checking
TL;DR: Model checking tools, created by both academic and industrial teams, have resulted in an entirely novel approach to verification and test case generation that often enables engineers in the electronics industry to design complex systems with considerable assurance regarding the correctness of their initial designs.
Book ChapterDOI
Symbolic Model Checking without BDDs
TL;DR: This paper shows how boolean decision procedures, like Stalmarck's Method or the Davis & Putnam Procedure, can replace BDDs, and introduces a bounded model checking procedure for LTL which reduces model checking to propositional satisfiability.
Proceedings ArticleDOI
Symbolic model checking using SAT procedures instead of BDDs
TL;DR: This paper applies bounded model checking to equivalence and invariant checking and presents several optimizations that reduce the size of generated propositional formulas in hardware verification.
Book ChapterDOI
Symbolic Reachability Analysis Based on SAT-Solvers
TL;DR: This paper shows how to adapt standard algorithms for symbolic reachability analysis to work with SAT-solvers and shows that even with relatively simple techniques it is possible to verify systems that are known to be hard for BDD-based model checkers.
Book ChapterDOI
SAT-Based Verification without State Space Traversal
Per Bjesse,Koen Claessen +1 more
TL;DR: This paper converts van Eijk's algorithm to use a SAT-solver instead of BDDs, and makes a number of improvements to the original algorithm, such as combining it with recently developed variants of induction.