Patent
Circuit for allocating memory cycles to two processors that share memory
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TLDR
In this article, a circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures, Code Idle and Code Release, where the control memory of a processor selects the process by two bits called code idle and code release.Abstract:
A circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures. In one procedure, control of memory is transferred only after a request for memory access has been made. In a second procedure, transfer of memory control to a requesting processor is automatically accompanied by a request to return control. The control memory of a processor selects the process by two bits called Code Idle and Code Release. Code Idle accompanies instructions that usually mean that the releasing processor will not need memory for several memory cycle times, and an explicit request for transfer is made when memory is actually needed. Code Release accompanies instructions that do not require memory access at the time but are typically followed by a memory request within a processor cycle time or a few processor cycle times. Memory control is returned without the delay that is associated with an explicit request.read more
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References
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Patent
Multiple microprocessor intercommunication arrangement
TL;DR: In this article, a communication arrangement between two or more independently operable microprocessor units (MPUs) is presented, where a plurality of MPUs sequentially access, under the control of a synchronous clock, a common memory for random access to blocks of memory for writing data therein or for reading data previously written therein without the necessity for contention resolution.
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TL;DR: In this paper, a microcomputer system consisting of two microcomputers, a read only memory (hereinafter abbreviated as "ROM") and a random access memory is described.
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