Patent
Clock synchronizing apparatus and method using frequency dependent variable delay
TLDR
In this article, a clock signal generator providing an output clock signal synchronized with an input clock signal having a frequency dependent variable delay line to accommodate a wide range of operating frequencies is presented.Abstract:
A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate a wide range of operating frequencies. A clock signal synchronized with an input clock signal propagated through an input time delay and an output time delay is generated by delaying an input buffered clock signal by a first time delay based on the frequency of the input buffered clock signal, and further delaying the delayed input buffered clock signal by a second time delay to compensate for timing skew introduced by the input time delay, the output time delay and the process of delaying the input buffered clock signal.read more
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Patent
Multiple processor system and method including multiple memory hub modules
TL;DR: A processor-based electronic system includes several memory modules arranged in first and second ranks as discussed by the authors, and the data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules used to access the memory module in the first set.
Patent
Arbitration system and method for memory responses in a hub-based memory system
James W. Meyer,Cory Kanski +1 more
TL;DR: In this article, a memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses and a buffered queue coupled to the bypass path.
Patent
Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch
Tyler J. Gomm,Gary M. Johnson +1 more
TL;DR: In this paper, the tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single implementation.
Patent
Delay stage-interweaved analog DLL/PLL
Kang Yong Kim,Dong Myung Choi +1 more
TL;DR: In this article, a methodology for enabling the delay stages of an analog delay locked loop (DLL) or phase-locked loop (PLL) to be programmed according to the operating condition of the input reference clock is presented.
Patent
Method and system for terminating write commands in a hub-based memory system
TL;DR: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub as discussed by the authors, which is a special case of the memory access signals adapted to be applied to memory devices.
References
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Patent
Delay-locked loop with binary-coupled capacitor
TL;DR: In this article, a race detection circuit is used to compare the binary-coupled capacitors in a delay-locked loop to the input clock signal and the output clock signal.
Patent
Digital delay locked loop
TL;DR: In this paper, an improved edge-triggered fully digital delay-locked loop (DLL) is described, which maintains reliable synchronization from startup and in spite of system clock jitter.
Patent
Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
TL;DR: In this article, a clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the internal clock signal, and an error signal corresponding to the difference in phase between the two clock signals is applied to a differential amplifier where the error signal is offset by a value corresponding to delay of an external clock signals as it is coupled to the phase detector.
Patent
Digital dual-loop DLL design using coarse and fine loops
R. Jacob Baker,Feng Lin +1 more
TL;DR: In this paper, a dual-loop digital delay-locked loop (DLL) is proposed to provide robust operation and tight synchronization over a wide range of delay variations, which includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range.
Patent
Clock signal duty cycle correction circuit and method
TL;DR: In this article, the authors propose a duty cycle correction circuit that facilitates correction of clock signal duty cycles, including correcting for errors introduced by intervening devices in the clock signal distribution network.