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Patent

Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

TLDR
In this article, a novel charge transfer switch and associated clocking scheme is proposed to reduce the supply current required to operate the charge pump, which reduces the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other.
Abstract
An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

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Citations
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References
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Patent

Method and apparatus for controlling the output current provided by a charge pump circuit

TL;DR: In this paper, an integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if a source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source voltage to the memory array.
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TL;DR: In this paper, a multiple staged charge pump network with staggered clock phases for pumping a first voltage to a second voltage with high current capability is presented. But the network is not suitable for wireless communication.
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Plural Stage Voltage Booster Circuit With Efficient Electric Charge Transfer Between Successive Stages

TL;DR: In this article, the voltage at the control electrode side (NB) is raised by a capacitor configuration, and voltage stabilizing elements (QC) are connected in parallel to the electric charge transmit elements between the terminal side and the control electrodes side.
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TL;DR: In this paper, a voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes, in which M3 is configured as a diode.
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TL;DR: In this article, a substrate bias generator for an integrated circuit, metal-oxide-semiconductor (MOS) random access memory (RAM) is described, which includes two input terminals for receiving first and second trains of periodic pulses.