Patent
Communications control apparatus for the use with a cache store
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TLDR
In this article, a communications control apparatus prepares for the generation of an interrupt signal along with appropriate address signals to retrieve data information from the main memory store upon the request from the central processor.Abstract:
A communications control apparatus prepares for the generation of an interrupt signal along with appropriate address signals to retrieve data information from the main memory store upon the request from the central processor. During preparation time, a tag directory is searched for an indication that the data information required is presently in the cache store. If a comparison is made, a match signal is generated to prevent the generation of the interrupt signal. The communications control apparatus addresses the cache store to retrieve the data information for use by the processor.read more
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Cache memory utilizing selective clearing and least recently used updating
Ronald E Lange,Richard J Fisher +1 more
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References
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Patent
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TL;DR: In this article, a memory system is disclosed for use in a multiprocessing environment where each processor has associated with it a buffer memory and means are provided for one buffer to retain a modified copy of data.
Patent
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Patent
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TL;DR: In this paper, a matching between an effective address, identifying an addressed information block, and an associative array word directly energizes corresponding random access array locations which contain the information block.
Patent
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TL;DR: In this article, a virtual memory system consisting of a main storage and a smaller high speed buffer is described, where the TLAT is used to store the current virtual-to-real address translations in a Translation Look Aside Table (TLAT) and the buffer directory is maintained in a buffer directory.
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