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Patent

Continuously variable synchronizer apparatus

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TLDR
In this article, a phase detection circuit is used to detect the phase difference between a local master oscillator and the received data and provide a clock signal to be used by the remote data sending device in a system phase-locked loop using a slave oscillator.
Abstract
A system is illustrated for making sure that received data and the master clock are in the proper relationship even though temperature, voltage supplies and aging cause variable transmission time delays between the source of data and the local circuit. This proper relationship is accomplished by detecting the phase difference between a local master oscillator and the received data and providing a clock signal to be used by the remote data sending device in a system phase-locked loop using a slave oscillator and the previously mentioned phase detection circuit. The slave oscillator tracks the frequency of the master oscillator and the phase of the incoming data. Since a clock signal was previously required for prior art systems, this approach eliminates the return clock that was required if the cable length and the associated data signal delay parameters could vary.

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Citations
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Integrating phase detector

TL;DR: In this paper, an integrating phase detector includes a phase comparator and an integrating load impedance, which is coupled to the current output of the phase detector for directly integrating the current pulse and providing a DC voltage proportional to the phase difference between the first and second input signals.
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Method for encoder frequency shift compensation

TL;DR: In this paper, a method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency shift compensated clock using the repeatable frequencies.
References
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Patent

Signal detection apparatus

TL;DR: In this article, a phase detection function is obtained by performing two series retiming operations on a data input signal in accordance with a local clock and exclusive OR'ing the signals involved in the two retimings operations.
Patent

Onboard clock correction by means of drift prediction

TL;DR: In this article, an on-board satellite clock correction system of the type where phase errors between the satellite clock and a ground-based clock are determined and a clock correction value sent to the satellite is determined by curve-fitting the determined phase errors in accordance with a polynomial function.
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Phase synchronization system

TL;DR: In this article, the authors propose a closed loop technology for phase synchronization between a first message generator and a second message generator at the same time, in which a phase information message is transmitted from the first to the second and then returned from the second to the first signal generator.