Proceedings ArticleDOI
Design space exploration of present implementations for FPGAS
Mohamad Sbeiti,Michael Silbermann,Axel Poschmann,Christof Paar +3 more
- pp 141-145
TLDR
The results highlight that PRESENT is well suited for high-speed and high-throughput applications, especially its hardware efficiency, i.e. the throughput per slice, is noteworthy.Abstract:
In this paper we investigate the performance of the block cipher PRESENT on FPGAs. We provide implementation results of an efficiency (i.e. throughput per slice) optimized design and compare them with other block ciphers. Though PRESENT was originally designed with a minimal hardware footprint in mind, our results also highlight that PRESENT is well suited for high-speed and high-throughput applications. Especially its hardware efficiency, i.e. the throughput per slice, is noteworthy.read more
Citations
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Journal ArticleDOI
Lightweight Hardware Architectures for the Present Cipher in FPGA
TL;DR: The hardware implementations of Present, a standardized lightweight cipher called to overcome part of the security issues in extremely constrained environments, are discussed and the most representative realizations of this cipher are reviewed and two novel designs are presented.
Journal ArticleDOI
A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs
TL;DR: This work proposes an IP protection mechanism for FPGA designs at the level of individual IP cores, by making use of the self-reconfiguring capabilities of modern FPGAs and deploying a trusted third party to run a metering service, similar to the work of Giineysu et ah and Drimer et at
Proceedings ArticleDOI
Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers
Neil Hanley,Maire O'Neill +1 more
TL;DR: This paper provides the first comprehensive hardware architecture comparison between Clefia and Present, as well as a comparison with the current National Institute of Standards and Technology (NIST) standard, the Advanced Encryption Standard.
Proceedings ArticleDOI
Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher
TL;DR: A novel FPGA-based design for the lightweight block cipher PRESENT and its implementation results are presented, which allows to study area-performance trade-offs and thus constructing smaller or faster implementations.
Proceedings ArticleDOI
RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT
Elif Bilge Kavun,Tolga Yalcin +1 more
TL;DR: Two different FPGA implementations of the lightweight cipher PRESENT are proposed, which occupy only 83 and 85 slices and produce a throughput of 6.03 and 5.13 Kbps at 100 KHz system clock on a Xilinx Spartan XC3S50 device.
References
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Book ChapterDOI
PRESENT: An Ultra-Lightweight Block Cipher
Andrey Bogdanov,Lars R. Knudsen,Gregor Leander,Christof Paar,Axel Poschmann,Matthew Robshaw,Yannick Seurin,C. Vikkelsoe +7 more
TL;DR: An ultra-lightweight block cipher, present, which is competitive with today's leading compact stream ciphers and suitable for extremely constrained environments such as RFID tags and sensor networks.
Journal Article
PRESENT: An Ultra-Lightweight Block Cipher
Andrey Bogdanov,Lars R. Knudsen,Gregor Leander,Christof Paar,Axel Poschmann,Matthew Robshaw,Yannick Seurin,C. Vikkelsoe +7 more
TL;DR: In this paper, the authors describe an ultra-lightweight block cipher, present, which is suitable for extremely constrained environments such as RFID tags and sensor networks, but it is not suitable for very large networks such as sensor networks.
Book ChapterDOI
Very Compact FPGA Implementation of the AES Algorithm
Pawel Chodowiec,Kris Gaj +1 more
TL;DR: Specific features of Spartan II FPGAs enabling compact logic implementation are explored, and a new way of implementing MixColumnsand InvMixColumnstransformations using shared logic resources is presented.
Book ChapterDOI
AES on FPGA from the fastest to the smallest
Tim Good,Mohammed Benaissa +1 more
TL;DR: Two new FPGA designs for the Advanced Encryption Standard (AES) are presented, believed to be the fastest and the smallest, and includes support for continued throughput during key changes for both encryption and decryption which previous pipelined designs have omitted.
Journal Article
AES on FPGA from the fastest to the smallest
Tim Good,Mohammed Benaissa +1 more
TL;DR: In this paper, two new FPGA designs for the Advanced Encryption Standard (AES) are presented, the first achieving 25 Gbps throughput using a Xilinx Spartan-Ill (XC3S2000) device and the second achieving 22 Mbps.