Patent
Deterministic latency characterization and mitigation
TLDR
In this paper, a method for requesting use of a shared resource in a computer system is presented, in which the device requesting a resource can predict the need for the resource before the need actually arises, and the amount of local buffering required within the device is therefore chosen to accommodate only the random latency component.Abstract:
A method is provided of requesting use of a shared resource in a computer system. The method is suited to applications in which the device requesting use of the resource can predict the need for the resource before the need actually arises. A request for use of the resource is characterized by a latency between the request and a subsequent granting of the request. The latency has both a deterministic component and a non-deterministic component. In response to an initialization of the computer system, the deterministic component of the latency is measured. The use of the resource is then requested by the requesting device some predetermined time before the time at which the need for such use arises. The predetermined time corresponds to the deterministic component of the latency. The amount of local buffering required within the device is therefore chosen to accommodate only the random latency component.read more
Citations
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References
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Patent
Bus control system and method that selectively generate an early address strobe
TL;DR: In this paper, an improved bus architecture for use in a multi-processor computer system has a shared address bus and a shared data bus, and each memory module has at least two separate memory modules.
Patent
Bus grant prediction technique for a split transaction bus in a multiprocessor computer system
TL;DR: Early bus grant prediction as discussed by the authors combines the operating advantages of both a split transaction bus and a simple shared bus for data transfer and uses arbitration logic to determine whether or not the bus will be available at the time the requested data has been retrieved and is ready for transfer.
Patent
Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller
James P. Kardach,Sung-Soo Cho,Jim S. Cheng,Debra T. Cohen,John W. Horigan,Nader Raygani,Seyed Yahay Sotoudeh,David I. Poisner,Neil Songer +8 more
TL;DR: In this paper, a direct memory access (DMA) request passing protocol is implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.
Patent
Method and apparatus for presenting an access request from a computer system bus to a system resource with reduced latency
Brian A. Childers,Eric A. Baden +1 more
TL;DR: In this article, a controller is coupled to the queue and to the multiplexor, for initiating the loading of the access request information into the queue, and for initially causing the multiple-xor to supply, at the multipleaxor output, the access requests from the second input, and subsequently causing, after the access demands from the first input become available at the queue output, a multiplexer to supply at the M/M/M output, access request messages from the source input.
Patent
Method and apparatus for arbitrating among processors for access to a common bus
TL;DR: In this paper, a method and apparatus for arbitrating among a plurality of processors for access to a common system bus in a multi-processing system is provided, and the bus arbitrating method includes the steps of detecting a request signal from a processor requesting access to the system bus, checking the number of other processors in the system, providing access to system bus by considering a priority factor among competing processors, and providing access by considering only a fairness factor when the required number of processors requesting access is not below a predetermined number.