Patent
Device controller with a separate command path between a host and the device and a separate data path including a first in, first out memory between the host and the device
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TLDR
In this paper, a SCSI bus controller has a separate data path from the SCI bus to the host bus and a separate command path for use to communicate with a local microprocessor.Abstract:
A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system Commands and status are passed via the dual port RAM Data is passed through a FIFO The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequenceread more
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Patent
High speed peripheral interconnect apparatus, method and system
TL;DR: In this article, a multiple use core logic chip set (MOCS) is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (AGP) bus and host and memory buses, as a bridging between an additional registered peripheral component interconnect (RegPCI) bus, or as a primary PCI bus and an additional RegPCI bus.
Patent
Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer
TL;DR: In this paper, a bridge circuit is proposed for efficient data transfer between a first bus and a second bus in a computer system, where the bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus, and the prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests.
Patent
Programmably configurable host adapter integrated circuit including a RISC processor
Craig A. Stuber,Byron Arlen Young,Paresh M. Borkar,Stillman F. Gates,Douglas K. Makishima,Paul von Stamwitz +5 more
TL;DR: The host adapter integrated circuit as mentioned in this paper is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having an additional protocol over the second bus, and (ii) transferring information between the two buses.
Patent
Locked exchange FIFO
TL;DR: In this article, a FIFO with locked exchange capability is disclosed, and a difference counter maintains the difference between the number of writes to the queue and reads from the queue, as tracked by the counter is a measure of the utilization.
Patent
Personal computer with small computer system interface (SCSI) data flow storage controller capable of storing and processing multiple command descriptions ("threads")
TL;DR: In this article, the authors describe a personal computer using a small computer system interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices.
References
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Patent
Data error correction system
TL;DR: In this article, a data storage system has a plurality of individual data storage units, each of which can undergo unpredictable independent failure, and it is possible to reconstruct any one failed data sub-block of a related group using the other sub-blocks.
Patent
Data transfer control system
Seigo Suzuki,Keiji Uemori +1 more
TL;DR: A data transfer control system for controlling data transfer between a processor and an input/output device comprises a multi-layer stack for temporarily storing transfer data, such as a first-in-first-out stack or a last-in firstout stack; first and second up/down counters having a preset function and permitting any designated address at the stack to be varied as discussed by the authors.
Patent
Apparatus guaranteeing that a controller in a disk drive system receives at least some data from an invalid track sector
TL;DR: In this article, a sequence detected signal indicating that a synchronization sequence occurring at regular intervals in a stream of data has occurred or should have occurred is provided, which is called a timing apparatus.
Patent
Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
TL;DR: In this paper, a cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the host processor.
Patent
Buffer system for input/output portion of digital data processing system
TL;DR: In this paper, a data transfer system for use in transferring data between a memory and an input/output system in a digital data processing system is presented, which includes a plurality of buffers into which data can be loaded from either the memory or the input-output system, and a buffer control selects the buffer to be loaded, and control signals from the memory govern the transfer of data from the data into and out of the selected buffer.