Patent
Differential comparator and analog-to-digital converter comparator bank using the same
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TLDR
In this paper, a fully differential comparator is proposed, which includes a differential signal input, a differential reference input, and a differential output, which can be used in conjunction with a conventional resistor string found in the front end of a flash ADC.Abstract:
A fully differential comparator includes a differential signal input, a differential reference input, and a differential signal output. Identical first and second gain stages are used in the differential comparator that each have a first single-ended input, a second single-ended input, and a differential output. The first single-ended inputs from the first and second gain stages form the differential signal input of the differential comparator. The second single-ended inputs from the first and second gain stages form the differential reference input of the differential comparator. The differential outputs of the first and second gain stages are cross-coupled to form the differential signal output of the differential comparator. The differential comparator can be used in conjunction with a conventional resistor string found in the front end of a flash ADC, but in a novel manner that prevents undesirable loading effects, as well as other problems associated with prior art single-ended comparators.read more
Citations
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References
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Patent
Comparator with extended common-mode input voltage range
TL;DR: In this article, a comparator comprising two differential input stages (Q1 to Q4 and Q5 to Q8) which are connected in parallel and fed by a common constant circuit source (QB) whose current is passed either to both or only to the one or to the other differential input stage, depending on whether the common-mode input voltage of the comparator is within, above or below a voltage range that is between the voltage values of the two poles (VC, VE) of a supply voltage source (B).
Patent
CMOS differential comparator with offset voltage
TL;DR: In this paper, the offset voltage is impressed by the design of the transistors in complementary MOS technology, and a circuit arrangement is proposed to generate an impressed offset voltage for a differential comparator, where the geometries (W/L) of the input differential transistors (M1, M2, M11, M12) are designed symmetrically and the associated load transistors are designed asymmetrically.
Patent
Half-flash analog-to-digital converter using differential comparators and crossover switching
TL;DR: In this article, a resistor-string divided into plural sets of unit-resistors generates plural reference voltages for the upper bits, while each divided set generates plural references for the lower bits, and the final digital value is obtained by linking the upper and lower bits digital values.
Patent
Multistage offset-cancelled voltage comparator
TL;DR: In this paper, a multistage voltage comparator with multiplicative transfer stages between successive comparator stages is described, where each transfer stage includes capacitors connected between the outputs of one stage and the inputs of the next stage.
Patent
Analog/digital converter operating by the expanded parallel method
TL;DR: In this paper, the analog/digital converter assembly includes a first analog-digital converter having N-bit resolution, operating by the parallel method and having comparators, and an amplifier is connected downstream of the subtractor.