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Patent

Dynamic sense-refresh detector amplifier

TLDR
In this article, a dynamic sense-refresh detector amplifier consisting of a cross coupled MOS transistor pair and two sets of loadrefresh circuits which each include a capacitor and three MOS transistors is used to eliminate the negative effect of threshold voltage losses on noise margin.
Abstract
A dynamic sense-refresh detector amplifier consists essentially of a cross coupled MOS transistor pair and two sets of load-refresh circuits which each include a capacitor and three MOS transistors. The load-refresh circuits eliminate the negative effect of threshold voltage losses on noise margin by allowing the memory cell from which information is read out and sensed to be refreshed to full 1 and 0 levels. A control terminal of a transistor of each load-refresh circuit is coupled to the transistor of cross coupled pair not associated with that load-refresh circuit. In addition, a voltage clamping transistor is used with each load device to further increase operating noise margins. The dynamic operation of the amplifier allows for relatively low power dissipation.

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Citations
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Patent

Semiconductor memory device.

TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
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Semiconductor memory circuit

TL;DR: In this article, a memory cell transistor (30) has the gate terminal connected to the word line and the drain and source terminals connected between the bit line (20) and the column line (16).
Patent

Dynamic random access memory

TL;DR: A DRAM is operated based upon an external clock input, a column enable, and a row enable to access and row and column addresses are latched into buffers based upon the clock input.
Patent

Dual stage sense amplifier for dynamic random access memory

TL;DR: In this article, an additional sense amplifier (100) on each column of a dynamic random access memory (RAM) was introduced to improve the transfer of logic information from a selected memory cell (M) to the input/output line associated therewith.
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Systems and methods for producing oil and/or gas

TL;DR: In this paper, a system comprising a carbon disulfide formulation storage, a mechanism for releasing at least a portion of the CDS formulation into a formation, and a mechanism to create a pulse in the CCS formulation in the formation is described.
References
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Patent

Stored charge memory detection circuit

Y Yao
TL;DR: In this article, the bucket brigade sense amplifiers are used to charge the bit line capacitances of the bit lines of a memory cell to approximately half the voltage to which the selected cell capacitance can be charged.
Patent

Differential amplifier for sensing small signals

TL;DR: In this paper, a differential amplifier providing high gain and capable of handling small signals has a common constant current source to which two parallel branches or circuits are connected, each of the branches includes a controlled current source and an input dependent current source, such as a field effect transistor, with a capacitor connected to the common point between the controlled source and the input dependent source for providing an alternating current signal to a feedback circuit of the amplifier for latch operation.
Patent

Regeneration of dynamic monolithic memories

H Askin
TL;DR: In this article, an isolation transistor between the bit decoder and memory cell was proposed to reduce power requirements and noise, improving stability of the sense latch and increasing the speed of operation of the memory.
Patent

Dynamic sense-refresh detector amplifier

TL;DR: In this paper, a dynamic sense-refresh detector amplifier consists of a cross coupled MOS transistor pair and two sets of load-resh circuits which each include a capacitor and three MOS transistors.
Patent

High accuracy MOS comparator

TL;DR: In this paper, a capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets, and the comparator is set up for operation in the comparison period during which the input signals are compared.