FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Yaman Umuroglu,Nicholas J. Fraser,Giulio Gambardella,Michaela Blott,Philip H. W. Leong,Magnus Jahre,Kees Vissers +6 more
TLDR
In this article, the authors present FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture, with fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements.Abstract:
Research has shown that convolutional neural networks contain significant redundancy, and high classification accuracy can be obtained even when weights and activations are reduced from floating point to binary values. In this paper, we present FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture. By utilizing a novel set of optimizations that enable efficient mapping of binarized neural networks to hardware, we implement fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements. On a ZC706 embedded FPGA platform drawing less than 25 W total system power, we demonstrate up to 12.3 million image classifications per second with 0.31 {\mu}s latency on the MNIST dataset with 95.8% accuracy, and 21906 image classifications per second with 283 {\mu}s latency on the CIFAR-10 and SVHN datasets with respectively 80.1% and 94.9% accuracy. To the best of our knowledge, ours are the fastest classification rates reported to date on these benchmarks.read more
Citations
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A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing
TL;DR: The time-domain neural network (TDNN), which employs time- domain analog and digital mixed-signal processing (TDAMS) that uses delay time as the analog signal, is proposed, which exploits energy-efficient analog computing, but also enables fully spatially unrolled architecture by the hardware-efficient feature of TDAMS.
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Scalable high-performance architecture for convolutional ternary neural networks on FPGA
Adrien Prost-Boucle,Alban Bourge,Frédéric Pétrot,Hande Alemdar,Nicholas Caldwell,Vincent Leroy +5 more
TL;DR: This work presents a highly versatile FPGA friendly architecture for TNN in which it can vary both the number of bits of the input data and the level of parallelism at synthesis time, allowing to trade throughput for hardware resources and power consumption.
Proceedings ArticleDOI
FPGA-based CNN inference accelerator synthesized from multi-threaded C software
TL;DR: In this article, a deep learning inference accelerator is synthesized from a C-language software program parallelized with Pthreads, using the LegUp high-level synthesis (HLS) tool synthesizing threads into parallel FPGA hardware, translating software parallelism into spatial parallelism.
Journal ArticleDOI
Memristor-Based Binarized Spiking Neural Networks: Challenges and applications
TL;DR: The challenges that face the memristor-based acceleration of NNs and how binarized SNNs (BSNNs) may offer a good fit for these emerging hardware systems are explored.
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An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS
TL;DR: A mixed-signal binary convolutional neural network (CNN) processor for always-on inference applications that achieves 3.8 mW per classification, an improvement over the previous low-energy benchmark on CIFAR-10, achieved in part by sacrificing some programmability.
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