PROBLEM TO BE SOLVED: To reduce a layout area, and to reduce power consumption in the transition of a clock signal by reducing the number of MOS transistors of a flip flop circuit. SOLUTION: A P channel MOS transistor 11 and an N channel MOS transistor 12 respectively connected to an internal normal rotation clock node ck and an internal inversion clock node ckb are shared by a try state inverter 1 included in a master latch and a try state inverter 5 included in a slave latch. COPYRIGHT: (C)2004,JPO

PROBLEM TO BE SOLVED: To prevent deterioration in imprint characteristics of a ferroelectric capacitor in a semiconductor integrated circuit in which data signals of a latch circuit are held in the ferroelectric capacitor. SOLUTION: The semiconductor integrated circuit has a latch circuit 10 provided with a signal holding part 12 for holding data signals D, and ferroelectric capacitors F1, F2 electrically connected to the signal holding part 12 via switches TR1, TR2. Only during a prescribed period, the switches TR1, TR2 are turned on so as to hold a remanent polarization corresponding to potential of the data signal D in the ferroelectric capacitors F1, F2. COPYRIGHT: (C)2009,JPO&INPIT

Flip-flop circuit and shift register

Semiconductor integrated circuit

In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.

Master slave flip-flop with low power consumption

A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Flip-flop circuit

The invention relates to a low-power master-slave flip-flop. In the master-slave flip-flop, a master latch has a first three-state level, a second three-state level and a first feedback level, and a slave latch has a third three-state level, a fourth three-state level and a second feedback level. A first clock switch and a second clock switch with opposite phases are provided. The first clock switch is configured in one of the first three-state level and the fourth three-state level, and the other of the first three-state level and the fourth three-state level shares the first clock switch. The second clock switch is configured in one of the second three-state level and the third three-state level, and the other of the second three-state level and the third three-state level shares the second clock switch. The second three-state level is provided with an additional pair of complementary devices, and the complementary devices have signal paths connected with each other in series, and are gated by data output of the slave latch. According to the low-power master-slave flip-flop, the number of the clock switches and the power consumption of the clock switches are reduced.

Low-power master-slave flip-flop

A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.

Flip-flop circuit and shift register

Citations

Semiconductor integrated circuit

Master slave flip-flop with low power consumption

Flip-flop circuit

Low-power master-slave flip-flop

Multi-bit flip-flop with shared clock switch

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