Patent
Flip-flop having improved synchronous reset
TLDR
In this paper, a flip-flop is provided having a data gate circuit for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data.Abstract:Â
A flip-flop is provided having a data gate circuit means (1) for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data. A master circuit means (2) is coupled to the data gate circuit means for receiving a clock pulse and for latching the internal data signals during a predetermined portion of the clock pulse. A slave circuit means (3) is coupled to the master circuit means for storing the internal data signals. A reset means (23) supplies a synchronous reset signal to the master circuit means for resetting the first and second complementary internal data signals on the occurrence of the next clock pulse.read more
Citations
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References
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Patent
Noise rejection Set-Reset Flip-Flop circuitry
TL;DR: Set-Reset Master-Slave Flip-Flop circuitry as mentioned in this paper uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that only signals applied to set-and reset terminals which are of the appropriate state at least prior to and during the transition of a clock signal from low to high state cause the output terminals of the flip-flop to be set to or maintained in preselected levels.
Patent
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TL;DR: In this article, a TTL flip-flop with improved AC and DC characteristics is provided including a higher resistance to output degradation and a quicker transition time from a high state to a low state.