Patent
Gate array basic cell
TLDR
In this paper, a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOS-FET is connected to the gate gate of the other circuit of N channel MCMOS-FCET is discussed.Abstract:
There is disclosed a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOSFET is connected to the gate of a MOSFET of the other circuit of the P channel MOSFET, and the gate of a MOSFET of one circuit of the N channel MOSFET is connected to the gate of a MOSFET of the other circuit of the N channel MOSFET.read more
Citations
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Patent
Gate array architecture
TL;DR: In this paper, a gate array architecture of transistors in the substrate of an integrated circuit is described, which includes at least one base site being three tracks wide and including four N-type transistors and four P-types transistors.
Patent
Field programmable gate array
Laurence H. Cooke,David Marple +1 more
TL;DR: In this paper, a FPGA matching the organization and performance of mask programmable gate arrays is presented, where the core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks.
Patent
Master slice LSI and layout method for the same
TL;DR: In this paper, a master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC, in which a plurality of gate basic cells are arranged on the semiconductor chip and a wiring channel grid having non-uniform pitches is defined on the gate Basic cells.
Patent
Gate array device having a memory cell/interconnection region
TL;DR: In this paper, a gate array device includes a plurality of basic cell regions spaced apart from one another to define intermediate regions therebetween, each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly.
Patent
Output buffer circuit that can be shared by a plurality of interfaces and a semiconductor device using the same
TL;DR: In this article, the transistors are arranged in series between the output power supply voltage and the output ground voltage, resulting in an output buffer circuit corresponding to a LVTTL.
References
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Patent
Gate array lsi device
TL;DR: In this paper, the authors proposed to enable the titled device of high performance to be easily obtained by shortening the wiring length by increasing the degree of freedom in wiring design with the third layer wirings.
Patent
CMOS/SOS transistor gate array apparatus
TL;DR: In this article, a universal gate array is illustrated using a specific pattern of CMOS transistors in an array which provides a high degree of board utilization in the layout of small runs of integrated circuits where the high cost of completely customized boards is unacceptable.
Patent
Semiconductor integrated circuit device
TL;DR: In this paper, the authors proposed a method to obtain a master slice system semiconductor integrated circuit device enabled to enhance a coefficient of cell utilization, and enabled to check a rise in cost by a method wherein an input/output buffer control circuit and an inside cell part are so constructed as to have versatility mutually.
Patent
Aluminum alloy composition body for producing aluminum container composition body from scrap and method thereof
TL;DR: In this paper, a mixture of aluminum scrap, including consumer scrap, plant scrap, and can making scrap is heated to form a melt composition, which is suitable for fabrication into sheet having strength and formability properties making it suitable for container manufacture.