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Figure 2. The structure of a scheduler using both hard constraints and soft constraints.
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Journal Article
•
DOI
•
High-Level Synthesis for FPGAs: From Prototyping to Deployment
[...]
Jason Cong
,
Bin Liu
,
Stephen Neuendorffer
1
,
Juanjo Noguera
1
,
Kees Vissers
1
,
Zhiru Zhang
- Show less
+2 more
•
Institutions (1)
Xilinx
1
01 Apr 2011
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems