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Proceedings ArticleDOI

Implementation of Blake 256 hash function for password encryption and parallel CRC

01 Oct 2015-pp 1-4
TL;DR: The Verilog description and hardware implementation on Altera DE2115 board of password encryption using Blake 256 cryptographic hash function coupled and parallel CRC for high performance, transmission error control is presented.
Abstract: One of the major sources of information in recent times is the internet, which facilitates the exchange of information between thousands of people at any instant. The transmission of sensitive data such as passwords must be accompanied by some form of robust protection to ensure prevention of unauthorized access. The requirement of strong encryption algorithms is of utmost importance. In this paper we present the Verilog description and hardware implementation on Altera DE2115 board of password encryption using Blake 256 cryptographic hash function coupled and parallel CRC for high performance, transmission error control.
Citations
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Proceedings ArticleDOI
01 Apr 2017
TL;DR: Creating a high secure password can achieve high level of security in authenticating the user over the internet and reduce the probability of hacking.
Abstract: Password thefts, a serious security threat to Internet users where the perpetrator steals the secure password and misuses it which makes the individual look like legitimate user, in an order to gather personal and financial information. It is important to prevent such identity theft attacks especially in fund transfer. One of the ways to prevent the password theft is to authenticate the user. Creating a high secure password can achieve high level of security in authenticating the user over the internet. Using the instant mailing service available in internet, user will obtain the public key. Then the private key is shared using secure server client connection ensuring legitimate user receives the private key. Both the keys are generated as RSA Tokens using Random password number Generator which are synchronized between server and client and the login expires once the current time limit exceeds the access time. The main aim is to use session login narrowing the login time thereby reducing the probability of hacking. These algorithms are very economical to implement provided they are time synchronized with the user.

7 citations


Cites methods from "Implementation of Blake 256 hash fu..."

  • ...[10] Password Encryption using parallel CRC....

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  • ...In [10] password transmission is secured by using utmost secure algorithm like BLAKE 256 Hash functions....

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Proceedings ArticleDOI
01 Jun 2018
TL;DR: A system that will secure the data throughout the migration process and the implementations and performance improvements of the parallel implementation are detailed.
Abstract: Clouds have offered users a very rich and flexible internet computing experience. Therefore, many individuals, companies, organizations and institutions migrated from traditional local computing services to the cloud environment. Despite the numerous benefits of cloud computing, there are still major concerns when it comes to security. Among the major security vulnerabilities is the migration process from the physical local servers to the cloud servers. During this migration, data can be lost due to corruption, incomplete transmission and interception. To address these threats, we have designed and implemented a system that will secure the data throughout the migration process. The method being implemented combines different security techniques to ensure that data is fully transferred from the source non-cloud computing environment to the cloud servers without being corrupted or intercepted by a malicious third party. The combination of data segmentation, error control/correction, encryption, decryption and hashing of data, which are applied in our system will ensure that the highest level of data security during the migration process is attained. However, due to the associated heavy computation processes, the whole system can slow down, which can result in poor and inefficient performance. Most chips today are multicore and parallelization, therefore, can be leveraged to enhance the overall system performance and efficiency. In this research, we detail the security improvements of our system and demonstrate the implementations and performance improvements of the parallel implementation.

4 citations


Cites methods from "Implementation of Blake 256 hash fu..."

  • ...The authors in [25] presented the Verilog description and hardware implementation on Altera DE2115 board of password encryption using Blake 256 cryptographic hash function coupled and parallel CRC for high performance, transmission error control....

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Proceedings ArticleDOI
06 Jul 2019
TL;DR: A hardware implementation of BLAke2 is elaborated on, using custom SIMD instructions that correspond to vital steps in the computation of a BLAKE2 digest.
Abstract: Hashing algorithms, the corner stone in a cryptographer's armory, are used in innumerable real life situations to protect critical information. The hashing function transforms the base information into an incomprehensible form. Such algorithms are also used for data integrity verification using checksums and quick retrieval of objects from a database. Some of the popular hashing algorithms are MD5, SHA-1, 2, 3. A hardware implementation of BLAKE2 is elaborated on, using custom SIMD instructions. These custom SIMD instructions correspond to vital steps in the computation of a BLAKE2 digest. Along with a slew of common arithmetic instructions - they coalesce into a 32-bit processor capable of carrying out BLAKE2 computations.

1 citations


Cites methods from "Implementation of Blake 256 hash fu..."

  • ...m0[127:0] = {m[s[0]], m[s[2]], m[s[4]], m[s[6]]} (2)...

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  • ...For instance, to obtain m0[127:0] in (2), the index values s[0], s[2], s[4], s[6] are sent as operands to the VINDEX function....

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  • ...STCMEM VR6, 5[VR4]//s[4],s[5],s[6],s[7] 7....

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  • ...Floyd Fernandes et al [4] proposed a Verilog description and hardware implementation of BLAKE 256 cryptographic hash function coupled with a parallel CRC on Altera DE2115....

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  • ...v = G(v,2,6,10,14,m[s[4]],m[s[5]]) 18....

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Journal ArticleDOI
TL;DR: In this article , a compact message permutation scheme was proposed to reduce the area and energy consumption of the fully pipelined BLAKE-256/512 accelerator, which includes two novel optimization techniques: register optimization and XOR optimization.
Abstract: Developing a low-cost and high-performance BLAKE accelerator has recently become an attractive research trend because the BLAKE algorithm is important in widespread applications, such as cryptocurrencies, data security, and digital signatures. Unfortunately, the existing BLAKE circuits are limited in performance and hardware efficiency. Therefore, this paper introduces the first fully pipelined BLAKE-256/512 accelerator to improve throughput and hardware efficiency. Moreover, based on the rates of changed words in consecutive message inputs, a compact message permutation scheme is proposed to reduce the area and energy consumption of the fully pipelined BLAKE-256/512 accelerator. To achieve these goals, the compact message permutation scheme includes two novel optimization techniques: register optimization, reducing the number of registers used by over 80% compared to conventional message permutation in a theoretical evaluation, and XOR optimization, decreasing the number of XOR gates by 93.8%. An ASIC-based experiment shows that the proposed compact message permutation scheme helps reduce the area and power consumption by up to 11.35% and 21.10%, respectively, for the fully pipelined BLAKE-256 accelerator and by up to 9.86% and 20.32%, respectively, for the fully pipelined BLAKE-512 accelerator. The correctness of the compact message permutation scheme is verified on a real hardware platform (an Alveo U280 FPGA).
Proceedings ArticleDOI
22 Aug 2022
TL;DR: Experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.
Abstract: Developing flexible and energy-efficient BLAKE-256/2s hardware has recently become necessary since BLAKE-256 and BLAKE2s are important cryptographic hash functions in reliability and security enhancement for blockchain-based IoT applications. However, previous BLAKE-256/2s architectures are challenging in achieving high flexibility and energy efficiency. Therefore, this paper proposes the BLAKE-256/2s co-processor to achieve high flexibility and energy efficiency for blockchain-based IoT applications. The proposed BLAKE-256/2s accelerator has three novel optimization techniques to achieve those goals. First, a configurable hashing core is proposed to enhance flexibility. Second, a pipelined permutation and compression architecture are developed to improve the throughput and hardware efficiency. Third, a mining transmission mechanism is introduced to optimize the performance of our co-processor at the system-on-chip level. The proposed co-processor is implemented and verified on a Xilinx Zynq $\mathbf{UltraScale}+$ MPSoC ZCU102 FPGA. Accordingly, the power and energy efficiency of the co-processor on the ZCU102 FPGA is significantly better than the Intel i9 10940X CPU and the RTX 3090 GPU. Moreover, experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.
References
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Proceedings ArticleDOI
28 Jun 2004
TL;DR: A polynomial selection process for embedded network applications is described and a set of good general-purpose polynomials are proposed that provide good performance for 3- to 16-bit CRCs for data word lengths up to 2048 bits.
Abstract: Cyclic redundancy codes (CRCs) provide a first line of defense against data corruption in many networks. Unfortunately, many commonly used CRC polynomials provide significantly less error detection capability than they might. An exhaustive exploration reveals that most previously published CRC polynomials are either inferior to alternatives or are only good choices for particular message lengths. Unfortunately these shortcomings and limitations often seem to be overlooked. This paper describes a polynomial selection process for embedded network applications and proposes a set of good general-purpose polynomials. A set of 35 new polynomials in addition to 13 previously published polynomials provides good performance for 3- to 16-bit CRCs for data word lengths up to 2048 bits.

393 citations


"Implementation of Blake 256 hash fu..." refers methods in this paper

  • ...[0] = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 [1] = 14 10 4 8 9 15 13 6 1 12 0 2 11 7 5 3 [2] = 11 8 12 0 5 2 15 13 10 14 3 6 7 1 9 4 [3] = 7 9 3 1 13 12 11 14 2 6 5 10 4 0 15 8 [4] = 9 0 5 7 2 4 10 15 14 1 11 12 6 8 3 13 [5] = 2 12 6 10 0 11 8 3 4 13 7 5 15 14 1 9 [6] = 12 5 1 15 14 13 4 10 0 7 6 3 9 2 8 11 [7] = 13 11 7 14 12 1 3 9 5 0 15 4 8 6 2 10 [8] = 6 15 14 9 11 3 0 8 12 2 13 7 1 4 10 5 [9] = 10 2 8 4 7 6 1 5 15 11 9 14 3 12 13 0...

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  • ...In this paper we have implemented the 8FDB polynomial described in [7]....

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01 Jan 2008
TL;DR: BLAKE is the proposal for SHA-3 that uses the HAIFA iteration mode and builds its compression function on the ChaCha core function, and resists generic second-preimage attacks, length extension, and sidechannel attacks.
Abstract: BLAKE is our proposal for SHA-3. BLAKE entirely relies on previously analyzed components: it uses the HAIFA iteration mode and builds its compression function on the ChaCha core function. BLAKE resists generic second-preimage attacks, length extension, and sidechannel attacks. Theoretical and empirical security guarantees are given, against structural and differential attacks. BLAKE hashes on a Core 2 Duo at 12 cycles/byte, and on a 8-bit PIC microcontroller at 400 cycles/byte. In hardware BLAKE can be implemented in less than 9900 gates, and reaches a throughput of 6 Gbps. FHNW, Windisch, Switzerland, jeanphilippe.aumasson@gmail.com ETHZ, Zurich, Switzerland, henzen@iis.ee.ethz.ch FHNW, Windisch, Switzerland, willi.meier@fhnw.ch Loughborough University, UK, r.phan@lboro.ac.uk

236 citations


"Implementation of Blake 256 hash fu..." refers background or methods in this paper

  • ...In a scheme, the transmitter sends the original data, then attaches a fixed number of check bits which are derived from the data bits by some deterministic algorithm [4]....

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  • ...[0] = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 [1] = 14 10 4 8 9 15 13 6 1 12 0 2 11 7 5 3 [2] = 11 8 12 0 5 2 15 13 10 14 3 6 7 1 9 4 [3] = 7 9 3 1 13 12 11 14 2 6 5 10 4 0 15 8 [4] = 9 0 5 7 2 4 10 15 14 1 11 12 6 8 3 13 [5] = 2 12 6 10 0 11 8 3 4 13 7 5 15 14 1 9 [6] = 12 5 1 15 14 13 4 10 0 7 6 3 9 2 8 11 [7] = 13 11 7 14 12 1 3 9 5 0 15 4 8 6 2 10 [8] = 6 15 14 9 11 3 0 8 12 2 13 7 1 4 10 5 [9] = 10 2 8 4 7 6 1 5 15 11 9 14 3 12 13 0...

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  • ...The two main versions of BLAKE are BLAKE- 256 and BLAKE -512 for 16 bit and 32 bit respectively....

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  • ...CRC gives tradeoff between adaptability, execution and expense has been taken more distant than those empowered by conventional heterogeneous architectures taking into account chip, DSP. Parallel CRC with BLAKE-256 gives efficient way of detection and encryption of data input....

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  • ...Blake 256 Hash function BLAKE [4] was one of the best five finalists in the the NIST SHA-3 Competition, made by Jean-Philippe Aumasson, Luca Henzen, Willi Meier, and Raphael C....

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