Proceedings ArticleDOI
Implementation of Blake 256 hash function for password encryption and parallel CRC
Floyd Fernandes,Ritu Gupta,S. Sivanantham,K. Sivasankaran +3 more
- pp 1-4
TLDR
The Verilog description and hardware implementation on Altera DE2115 board of password encryption using Blake 256 cryptographic hash function coupled and parallel CRC for high performance, transmission error control is presented.Abstract:
One of the major sources of information in recent times is the internet, which facilitates the exchange of information between thousands of people at any instant. The transmission of sensitive data such as passwords must be accompanied by some form of robust protection to ensure prevention of unauthorized access. The requirement of strong encryption algorithms is of utmost importance. In this paper we present the Verilog description and hardware implementation on Altera DE2115 board of password encryption using Blake 256 cryptographic hash function coupled and parallel CRC for high performance, transmission error control.read more
Citations
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Proceedings ArticleDOI
Application of session login and one time password in fund transfer system using RSA algorithm
TL;DR: Creating a high secure password can achieve high level of security in authenticating the user over the internet and reduce the probability of hacking.
Proceedings ArticleDOI
Optimizing Performance in Migrating Data between Non-cloud Infrastructure and Cloud Using Parallel Computing
Mimouna Alkhonaini,Hoda El-Sayed +1 more
TL;DR: A system that will secure the data throughout the migration process and the implementations and performance improvements of the parallel implementation are detailed.
Proceedings ArticleDOI
Implementation of SIMD Instruction Set Extension for BLAKE2
V Ganesh,B.V.H Sandilya +1 more
TL;DR: A hardware implementation of BLAke2 is elaborated on, using custom SIMD instructions that correspond to vital steps in the computation of a BLAKE2 digest.
Journal ArticleDOI
Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator
TL;DR: In this article , a compact message permutation scheme was proposed to reduce the area and energy consumption of the fully pipelined BLAKE-256/512 accelerator, which includes two novel optimization techniques: register optimization and XOR optimization.
Proceedings ArticleDOI
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications
TL;DR: Experimental results on several FPGAs prove that the proposed co-processor is considerably higher throughput, area efficiency, and flexibility than FPGA-based related works.
References
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Proceedings ArticleDOI
Cyclic redundancy code (CRC) polynomial selection for embedded networks
Philip Koopman,T. Chakravarty +1 more
TL;DR: A polynomial selection process for embedded network applications is described and a set of good general-purpose polynomials are proposed that provide good performance for 3- to 16-bit CRCs for data word lengths up to 2048 bits.
SHA-3 proposal BLAKE
TL;DR: BLAKE is the proposal for SHA-3 that uses the HAIFA iteration mode and builds its compression function on the ChaCha core function, and resists generic second-preimage attacks, length extension, and sidechannel attacks.