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Patent

Improved handling of the results of speculatively executed jobs in a multiprocessing system

Holmberg Per Anders, +3 more
TLDR
In this article, a private memory buffer is allocated for holding results, such as a communication message, an operation system call or a new job signal, of a speculatively executed job.
Abstract: 
In general, the invention is directed towards a multiprocessing system in which jobs are speculatively executed in parallel by multiple processors (30-1, 30-2, ..., 30-N). By speculating on the existence of more coarse-grained parallelism, so-called job-level parallelism, and backing of to sequential execution only in cases where dependencies that prevent parallel execution of jobs are detected, a high degree of parallelism can be extracted. According to the invention a private memory buffer is speculatively allocated for holding results, such as a communication message, an operation system call or a new job signal, of a speculatively executed job, and these results are speculatively written directly into the allocated memory buffer. When commit priority is assigned to the speculatively executed job, a pointer referring to the allocated memory buffer is transferred to an input/output (10) device which may access the memory buffer by means of the transferred pointer. In this way, by speculatively writing messages and signals into private memory buffers, even further parallelism can be extracted.

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Patent

Processor system and accelerator

Hironori Kasahara, +1 more
TL;DR: In this article, a processor system comprising at least one processor core including a processor, a memory and an accelerator is provided, and the accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written.
Patent

Advance cache allocator

Sushma Wokhlu, +4 more
TL;DR: In this article, a technique for advance cache allocation is described, which can include selecting a job from a plurality of jobs, selecting a processor core from the plurality of processor cores to execute the selected job, receiving a message which describes future memory accesses that will be generated by the selected jobs, generating a memory burst request based on the message, and performing the memory burst requests to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core.
References
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Patent

Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit

Bartholomew Blaner, +3 more
Abstract: The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
Patent

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Bradley D. Hoyt, +7 more
TL;DR: In this article, a branch instruction resolution system for a pipelined processor is described, in which a first stage predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions.
Patent

Speculative execution processor

Kozo Kimura, +2 more
TL;DR: In this paper, a speculative execution processor with a plurality of executing units for processing in parallel the plurality of instructions in an instruction sequence stored in its memory is described, which includes an instruction type distinguishing device for distinguishing a type of a conditional branch instruction included in the unexecuted instruction sequence, the condition of the conditional branch instructions depending on another instruction, an instruction parallelissuing device for issuing in parallel instructions included in a succeeding instruction sequence to be executed following the conditional branches instruction and/or instructions included by the executing units while whether or not to branch is not determined.
Patent

Instruction pointer limits in processor that performs speculative out-of-order instruction execution

Rohit A. Vidwans, +3 more
TL;DR: In this article, the authors propose a method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement operation.
Patent

Method for speculative calculation of physical register addresses in an out of order processor

Ramesh Panwar, +1 more
TL;DR: In this paper, a processor speculatively executes instructions which specify logical addresses and converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.