Iterative binary divider utilizing multiples of the divisor

TLDR: In this paper, a high speed divider is provided for a digital computer for generating a predetermined number of partial quotient bits per iteration by initially using a decode table implemented by a logic network to examine the high order bits of the divisor and another high order bit of the dividend, on the first iteration and on successive iterations, of the partial remainder.

Abstract: A high speed divider is provided for a digital computer for generating a predetermined number of partial quotient bits per iteration by initially using a decode table implemented by a logic network to examine a predetermined number of high order bits of the divisor and another predetermined number of high order bits of the dividend, on the first iteration, and on successive iterations, of the partial remainder. The decode table is generated using the principle that for a given range of the divisor and dividend, as established by fixing the high order digits thereof, a limited range of possible partial quotients exists. The number of difference networks required to form partial remainders is limited to the number of decoded possible values for the partial quotient to be generated. A number of trial possible partial remainders are generated by the difference networks using the multiples of the divisor equal to the decoded possible partial quotient values. A second decode table, implemented by a logic network, determines, from the multiples of the divisor gated to the difference networks, and the results determined therein, which has produced the new partial remainder for the next iteration. The bits of the partial quotient are determined by a selector which examines the multiples of the divisor gated to the difference networks and the network from which the new partial remainder was derived. The process of iteration continues until the entire quotient is generated.