Patent
Low latency integer divider and integration with floating point divider and method
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TLDR
In this paper, a method and device were proposed to determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend.Abstract:
A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and calculates NDQ number of quotient digits from the normalized divisor and dividend.read more
Citations
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Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations
TL;DR: In this article, a floating-point operand normalization circuit was proposed to generate NDQ digits from the normalized dividend and the normalized divisor provided by the normalization circuits.
Patent
Integer/floating point divider and square root logic unit and associates methods
TL;DR: In this paper, a shared hardware integer/floating point divider and square root logic unit is proposed, which combines floating point division, floating point square root operations, and integer division into one shared hardware design.
Patent
Integer division circuit with allowable error
TL;DR: In this article, an integer division circuit with allowable error is described, which includes a pointer, a first left shifter, a second left shifters, a subtractor, a multiplier, and a right shifter.
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Dividing device and dividing method
TL;DR: In this article, the mantissa parts of the dividend and the divisor were left-shifted by the shifting circuits and a subtracting circuit was used to output a resultant value.
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Fast integer division
TL;DR: In this article, a fast integer divider circuit with a plurality of adders is described, where each adder subtracts a multiple of the divisor from the current value in the partial remainder register.
References
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Patent
Floating point arithmetic unit using modified Newton-Raphson technique for division and square root
TL;DR: A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method is described in this paper.
Patent
Quotient digit selection logic for floating point division/square root
TL;DR: In this paper, an enhanced quotient digit selection function was proposed to prevent the working partial remainder from becoming negative if the result is exact, choosing a quotient of zero instead of a quantifier of one when the actual partial remainder is zero, which provides one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit.
Patent
Divider and method with high radix
TL;DR: In this article, the circuit scale of the quotient/remainder discriminating part of retracting divider for high-order radix was reduced by determining a quotient by performing bit matching corresponding to the compared results of a three-input adder/subtracter, a threeinput comparator and second and first comparators.
Proceedings ArticleDOI
167 MHz radix-8 divide and square root using overlapped radix-2 stages
J.A. Prabhu,G.B. Zyner +1 more
TL;DR: UltraSPARC's IEEE-754 compliant floating point divide and square root implementation is presented and the quotient selection logic is slightly modified to prevent the formation of a negative partial remainder for exact results.
Patent
Computer method and apparatus for division and square root operations using signed digit
TL;DR: In this article, an adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format.