Low power reconfigurable sub -band filter bank ASIC for MP3 decoder

TLDR: An IEEE 754 single precision floating-point runtime re-configurable architecture to reduce the power consumption of the filter bank in the audio decoder and achieves low powered decoding process without significantly compromising on the accuracy and speed.

Abstract: There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results of MP3 algorithm on ARM processors it has been observed that, the synthesis filter bank in the audio decoder consumes maximum power. Hence to reduce the power consumption of the filter bank, we developed an IEEE 754 single precision floating-point runtime re-configurable architecture. The proposed architecture consumes less power at run time as the last 12 bits of the mantissa part of the synthesis filter coefficients are zero most of the time and hence the corresponding multipliers will be switched off. Since the active multipliers during inverse polyphase quadrature mirror filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesized and simulated the architecture using 0.35 mum process technology under Synopsys environment. A uniform worst case power reduction of 23.7% has been achieved in the frequency range from 1MHz to 20 MHz when all the multipliers are in active state.