Showing papers in "International Journal of Circuit Theory and Applications in 2012"

Analysis of current–voltage characteristics for memristive elements in pattern recognition systems

Abstract: A topologically simple memristive-based oscillatory network showing a wide plethora of dynamical behaviors may be a good candidate for the realization of innovative oscillatory associative and dynamic memories for the recognition of spatial–temporal synchronization states. The design of such pattern recognition systems may not leave aside a preliminary thorough investigation of the nonlinear dynamics of the network and its basic components. In a synchronization scenario with almost-sinusoidal oscillations, each of the memristive elements used in the cells of the network under consideration features an unusual current–voltage behavior. This manuscript models the linear circuitry and the memristive element in each cell so as to capture the observed dynamics and then presents an analytical study explaining the quantitative dependence of memristive current–voltage behavior on excitation amplitude–angular frequency ratio and on initial condition on the system state. This work leads to the first rigorous classification of all possible current–voltage characteristics for a sine-wave voltage-driven memristive element. This analytical study shall pave way towards a better understanding of the complex and still unexplored dynamical properties of this nonlinear device, whose distinct features could improve the capabilities of future-generation pattern recognition systems. Copyright © 2012 John Wiley & Sons, Ltd.

Behavioral modeling of statistical phenomena of single-photon avalanche diodes

Abstract: In this paper, we present an accurate behavioral model for simulating single-photon avalanche diodes (SPADs). The device operation is described using the Verilog-A description language, which is an analog extension of the common digital hardware description language. The derived model is able to emulate the static, the dynamic behavior and the main statistical effects of an SPAD, such as the turn-off probability, the dark-count and the after-pulsing phenomena. Spectre simulations reveal the validity of the approach showing a good matching between the behavior of the proposed model and experimental results reported in the literature. Copyright © 2011 John Wiley & Sons, Ltd.

Power-efficient analog design based on the class AB super source follower

Abstract: A class AB version of the conventional super source follower (SSF) is described. The circuit greatly increases slew rate (SR) and current efficiency, maintaining the low distortion and low output resistance of the SSF. Class AB operation is achieved without extra power dissipation or supply requirements, and without bandwidth or noise degradation. The circuit can advantageously replace the SSF in a wide variety of analog systems, opening a new research line in analog design. To illustrate the widespread application of this cell, a class AB differential unity-gain buffer, a class AB differential current mirror and two class AB differential transconductors are designed, fabricated in a 0.5µm CMOS technology and tested. Measurement results using a dual supply of ±1.65V show that the proposed class AB version of the SSF improves SR by a factor 21.5 and increases bandwidth by 10%, keeping noise level, input range, power consumption, and supply requirements unaltered. The fabricated class AB current mirror features a THD at 100 kHz of − 62dB for signal currents 20 times larger than the bias current. The fabricated transconductors feature an IM3 at 1 MHz of − 56.6dB for output currents more than 13 times larger than the bias currents. Copyright © 2011 John Wiley & Sons, Ltd.

On global asymptotic stability for a class of delayed neural networks

Abstract: This paper deals with the problem of stability analysis for a class of delayed neural networks described by nonlinear delay differential equations of the neutral type. A new and simple sufficient condition guaranteeing the existence, uniqueness and global asymptotic stability of an equilibrium point of such a kind of delayed neural networks is developed by the Lyapunov–Krasovskii method. The condition is expressed in terms of a linear matrix inequality, and thus can be checked easily by recently developed standard algorithms. When the stability condition is applied to the more commonly encountered delayed neural networks, it is shown that our result can be less conservative. Examples are provided to demonstrate the effectiveness of the proposed criteria. Copyright © 2011 John Wiley & Sons, Ltd.

Low power Wallace multiplier design based on wide counters

Abstract: Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in today's designs and the future's designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multiplier's speed. This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high-order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Altera's Quartus-II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multiplier's size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers. Copyright © 2011 John Wiley & Sons, Ltd. (A new power aware multiplier design based onWallace tree is presented using high order counters. Multipliers of widths of 8, 16, and 32-bits are designed based on the proposed algorithm. Simulations showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multipliers size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers.)

Multiple catastrophic fault diagnosis of analog circuits considering the component tolerances

Abstract: This paper deals with the diagnosis of multiple catastrophic faults, being cuts (open-circuits) of some connecting paths and/or short-circuits of some pairs of points in analog circuits. A method enabling us to detect and identify the faults, taking into account the deviations of the circuit parameters within their tolerance ranges, is developed. The method exploits an appropriate fault dictionary. The fault dictionary is used only for preliminary identification of the faults, because it is based on the analysis of the circuits with nominal parameters. The crucial point of the method is a verification procedure, proposed in this paper, based on the linear programming approach. It leads to the results considering the component variations within their tolerance ranges. In addition, a procedure for selecting appropriate test points, employing some evolutionary techniques, is developed. Although the approach presented in this paper is described in detail for linear circuits, it can be directly generalized to nonlinear circuits. Three numerical examples, including two linear and one nonlinear circuits, illustrate the proposed method and show its efficiency. Copyright © 2011 John Wiley & Sons, Ltd.

An expression for the voltage response of a current-excited fractance device based on fractional-order trigonometric identities

Abstract: We report a closed-form expression of the voltage response of a current-excited fractance device. The derived simple expression is made possible following the introduction of the generalized sine and cosine functions (rmsinα(t) and cosα(t)), which are valid on any fractional-order surface and tend to the normal sin(t) and cos(t) at α = 1 or asymptotically as t→∞. Copyright © 2011 John Wiley & Sons, Ltd. (This paper reports a closed-form expression of the voltage response of a current excited fractance device. The derived simple expression is made possible following the introductionof the generalized sine and cosine functions which are valid on any fractionalorder surface and tend to the normal sine and cosine functions asymptotically as t→∞.)

Spiral periodic structure inside chaotic region in parameter-space of a Chua circuit

Abstract: In this letter we investigate, via numerical simulations, the parameter-space of the set of autonomous first-order differential equations of a Chua circuit. We show that this parameter-space presents self-organized periodic structures immersed in a chaotic region, forming a single spiral structure that coils up around a focal point. Additionally, bifurcation diagrams are used to show that those periodic structures also organize themselves in period-adding cascades, along specific directions that point towards this same focal point. Copyright © 2010 John Wiley & Sons, Ltd.

All-pass sections with rich cascadability and IC realization suitability

Abstract: In this paper, two new circuit configurations for realizing voltage-mode (VM) all-pass sections (APSs) are presented. The proposed circuits employ only two differential voltage current conveyors (DVCCs) and are cascadable with other VM circuits due to their high-input and low-output impedances. The first configuration uses a grounded resistor and a grounded capacitor without requiring matching constraints, whereas the second employs two grounded resistors and a grounded capacitor with a single matching condition. While the first configuration can realize only one all-pass response, the second can provide inverting and non-inverting all-pass responses with selection of appropriate input port. Adding two grounded resistors to the proposed filters, variable gain APSs can also be obtained. As applications, two quadrature oscillators, each of which using one of the proposed all-pass circuits, one grounded resistor and one grounded capacitor are presented. SPICE simulation results are included to verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.

Dynamics of PFC power converters subject to time-delayed feedback control

Abstract: Power factor correction converters are power electronics circuits used as AC-DC power supplies. These systems are well known to exhibit nonlinear phenomena such as subharmonic oscillations and chaotic regimes. These undesirable behaviors increase the THD and therefore can jeopardize enormously the system performances. In this paper, time delay feedback control is applied to stabilize a two-stage power factor correction AC-DC converter when it exhibits these instabilities under traditional controllers. This control technique introduces many advantages to the most and widely used average current mode control through widening the stability domain of the system. By appropriately selecting the time delay feedback gain and the time delay period, the undesirable subharmonic components are eliminated, whereas the desired ones remain unchanged. A harmonic balance approach is used for studying the dynamics of the system under the new control scheme and to obtain the stabilization domain. Copyright © 2010 John Wiley & Sons, Ltd.

Dynamic modeling of DC–DC converters with peak current control in double-stage photovoltaic grid-connected inverters

Abstract: In photovoltaic (PV) double-stage grid-connected inverters a high-frequency DC–DC isolation and voltage step-up stage is commonly used between the panel and the grid-connected inverter. This paper is focused on the modeling and control design of DC–DC converters with Peak Current mode Control (PCC) and an external control loop of the PV panel voltage, which works following a voltage reference provided by a maximum power point tracking (MPPT) algorithm. In the proposed overall control structure the output voltage of the DC–DC converter is regulated by the grid-connected inverter. Therefore, the inverter may be considered as a constant voltage load for the development of the small-signal model of the DC–DC converter, whereas the PV panel is considered as a negative resistance. The sensitivity of the control loops to variations of the power extracted from the PV panel and of its voltage is studied. The theoretical analysis is corroborated by frequency response measurements on a 230 W experimental inverter working from a single PV panel. The inverter is based on a Flyback DC–DC converter operating in discontinuous conduction mode (DCM) followed by a PWM full-bridge single-phase inverter. The time response of the whole system (DC–DC + inverter) is also shown to validate the concept. Copyright © 2011 John Wiley & Sons, Ltd.

Three novel improved CMOS C-multipliers

Abstract: Three novel improved CMOS capacitance scaling schemes are presented and compared with some conventional schemes. The novel topologies that use a modified second-generation current conveyor, an improved cascode current mirror and an OTA with two outputs connected in current steering configuration provide higher values of Q and better frequency responses than conventional structures using basic current mirror schemes, as the simple current mirror or cascode current mirrors. Simulation results and some measurements of a chip prototype are presented. Copyright © 2011 John Wiley & Sons, Ltd.

Energy-efficient single-clock-cycle binary comparator

Abstract: A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.

Design of Sinh-Domain filters using complementary operators

Abstract: A new systematic method for designing Sinh-Domain filters is introduced in this paper. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh-Domain. The proposed method offers the benefits of facilitating the design procedure of high-order Sinh-Domain filters and of the absence of any restriction concerning the type and/or the order of the realized filter function. As an example, a third-order Sinh-Domain leapfrog filter is designed by employing the proposed set of operators. Two possible realizations are given and their performance has been evaluated and compared through simulation results. Copyright © 2011 John Wiley & Sons, Ltd.

Improved static and dynamic performances of a two-cell DC–DC buck converter using a digital dynamic time-delayed control

Abstract: Multi-cell converters have been developed to overcome shortcomings in usual switching devices. The control system in these circuits is twofold: first, to balance voltages of the switches and second to regulate the load current to a desired value. However, with a purely proportional controller, the system presents a static error. With a PI controller the static error is annihilated, but at the expense of shortening the stability region and increasing settling time. In this work, a zero static error dynamic controller for a two-cell DC–DC buck converter is designed. To achieve zero current error, we propose a generalized scheme of a dynamic controller. Then, using nonlinear analysis and Lyapunov stability theory and bifurcation prediction tools, we prove that zero static error is achieved. The proposed controller outperforms the PI controller in terms of settling time in the presence of saturating effect during the start-up transients. Numerical simulations in the form of time domain waveforms and bifurcation diagrams from switched circuit-based model are presented to confirm our theoretical results. Copyright © 2010 John Wiley & Sons, Ltd. (Multi-cell converters have been developed to overcome shortcomings in usual switching devices. The control system in these circuits is twofold: first, to balance voltages of the switches and second to regulate the load current to a desired value. However, with a purely proportional controller, the system presents a static error. With a PI controller the static error is annihilated, but at the expense of shortening the stability region and increasing settling time. In this work, a zero static error dynamic controller for a two-cell DC-DC buck converter is designed. To achieve zero current error, we propose a generalized scheme of a dynamic controller. Then, using nonlinear analysis and Lyapunov stability theory and bifurcation prediction tools, we prove that zero static error is achieved. The proposed controller outperforms the PI controller in terms of settling time in the presence of saturating effect during the startup transients. Numerical simulations in the form of time domain waveforms and bifurcation diagrams from switched circuit-based model are presented to confirm our theoretical results.)

From energy-delay metrics to constraints on the design of digital circuits

Abstract: In this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energy-efficient design of digital CMOS very large-scale integrated circuits Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of EiDj metrics is typically adopted Physical interpretation and interesting properties for the designs minimizing EiDj metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints Two design examples in a 65-nm CMOS technology are also reported to exemplify the theoretical results Copyright © 2011 John Wiley & Sons, Ltd (The relation between general metrics of the energy-delay (E-D) tradeoff and the achievement of energy-efficiency in digital CMOS circuits is investigated Qualitative requirements in terms of Ei Dj products are translated into quantitative results in terms of transistors sizings corresponding to welldefined energy-to-delay sensitivities, while Logical Effort is employed to determine practical design constraints Two examples in a 65-nm technology are reported to exemplify the design framework Copyright © 2011 John Wiley & Sons, Ltd)

VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms

Abstract: In this paper, a low-complexity and highly integrated IP Core for image/video transformations is presented. It can perform quantized 8×8 DCT and quantized 8 × 8/4 × 4 H.264 integer transforms on the presented configurable architecture using integer shift–add arithmetic operations. The MPEG-4/H.264 experimental and circuit simulation results show that the reconfigurable modules and the CORDIC-Scaler can not only approximate the arbitrary scaling values for different video standards efficiently but also achieve very high throughput and retain good transformation quality compared with the default methods in terms of PSNR. Therefore, the proposed IP Core is very suitable for low-complexity multi-purpose Video Codecs in SoC designs. Copyright © 2011 John Wiley & Sons, Ltd.

Analytical synthesis and comparison of voltage-mode N th-order OTA-C universal filter structures

Abstract: Complementary single-ended-input operational transconductance amplifier (OTA)-based filter structures are introduced in this paper Through two analytical synthesis methods and two transformations, one of which is to convert a differential-input OTA to two complementary single-ended-input OTAs, and the other to convert a single-ended-input OTA and grounded capacitor-based one to a fully differential OTA-based one, four distinct kinds of voltage-mode nth-order OTA-C universal filter structures are proposed TSMC H-Spice simulations with 035µm process validate that the new complementary single-ended-input OTA-based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures Moreover, the new voltage-mode band-pass, band-reject and all-pass (except the fully differential one) biquad structures, all enjoy very low sensitivities Both direct sixth-order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency-dependent transconductance Copyright © 2010 John Wiley & Sons, Ltd

A comparative analysis and design of quantum-dot cellular automata memory cell architecture

Abstract: Quantum-dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.

Universal biquad filter topology using low-voltage current mirrors

Abstract: A single input multiple output biquad filter topology realized using current mirrors as active elements is introduced in this manuscript. The proposed topology simultaneously realizes all the standard transfer functions of a biquad filter without modifying its structure. Some attractive characteristics offered by the proposed topology are the employment of only grounded capacitors as passive elements, the electronic adjustment of the resonant frequency, and the capability for operation under a low-voltage environment. The operation of the proposed topology has been validated through simulation results, where the most important performance factors have been evaluated in the case of a bandpass filter transfer function. Copyright © 2010 John Wiley & Sons, Ltd.

Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

Abstract: The paper presents an algorithmic approach to a low-sensitivity design strategy for analog filter pairs based on a gyrator–capacitor prototype circuit. The general structure of the prototype circuit is proposed. It assumed that the generic structure of the prototype circuit can evolve, with the use of additional gyrators, into a circuit with increased redundancy. It is shown that symbolic analysis of the prototype circuit, used to formulate a set of nonlinear algebraic equations, is necessary to achieve a sufficiently high algorithm operation speed. To find a solution to this specific system of nonlinear algebraic equations, different numerical methods are compared. The modified Hooke and Jeeves algorithm is found to be the most effective. The elaborated algorithms and programs are illustrated with the seventh-order filter pair example. The obtained filter is better than the filter obtained using LC ladder structures with respect to chip area and power consumption, and these improvements are obtained without loss of sensitivity properties. Copyright © 2010 John Wiley & Sons, Ltd.

All-MOS implementation of RC networks for time-controlled Gaussian spatial filtering

Abstract: This paper addresses the design and VLSI implementation of MOS-based RC networks capable of performing time-controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2-node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analyzing them from a stochastic point of view. Following the design methodology proposed, the error committed by an MOS-based grid when compared with its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS-OPTO process. This prototype incorporates a focal-plane MOS-based RC network that performs fully programmable Gaussian filtering. Copyright © 2011 John Wiley & Sons, Ltd.

On the design of multi notch filters

Abstract: A methodology for designing FIR multi notch filters (NFs) derived from second-order prototype IIR NFs is suggested. Rejection bandwidth for the designed filter can be controlled by suitable choice of ‘r’, the pole radius of the IIR prototype NFs. The suggested multi NF can also be adapted to eliminate second-, third- and fourth-order harmonics of periodic noise besides the fundamental noise frequency component. A special case when two notch frequencies ω1 and ω2 are such that [(cosω1)(cosω2) = − 1/2] has also been discussed. The IIR multi NF design for this special case results in reduction of the number of multipliers without affecting the response of the desired NF. For the aforereferred condition, the required coefficients of impulse response of FIR multi notch filter get reduced to almost half in number resulting in reduced computations. The number of zero coefficients further reduces with increase in ‘r’ value. In addition, the frequency response becomes better, with reduced ripples in the pass bands, when ‘r’ is increased and length ‘L’ of the FIR NF is chosen appropriately. Copyright © 2010 John Wiley & Sons, Ltd.

An inductorless CMOS quadrature oscillator continuously tuneable from 3.1 to 10.6 GHz

Abstract: Modern RF front-ends require wide tuning-range oscillators with quadrature outputs. In this paper we present a two-integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013mm2, leading to a figure-of-merit FOMA of −176.7dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency. Copyright © 2010 John Wiley & Sons, Ltd. (We present a two-integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013 mm2, leading to a figure-of-merit FOMA of −176.7 dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency.)

FDCCII-based electronically tunable voltage-mode biquad filter

Abstract: In this work, a voltage-mode biquad filter realizing low-pass, band-pass and high-pass characteristics is presented. The proposed filter, which employs two FDCCIIs, two grounded capacitors and two NMOS transistors, provides electronic tunability with the control voltage applied to the gate. NMOS transistors act as linear resistor. Furthermore, the proposed circuit still enjoys realization using a low number of active and passive components, no requirement with the component choice conditions to realize specific filtering functions, high input impedance, and low active and passive sensitivities performance. Simulation results using SPICE program are given to show the performance of the filter and verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.

A novel energy-retaining inverter for AC arc welding machines

Abstract: A novel energy-retaining power supply for AC arc welding machines is proposed in this paper. In this kind of power supply, current-steering diodes connected across the output chokes keep the inductor current continuous and retain the energy during the commutation period, hence reducing the commutation time to ensure a better welding performance. In addition, the stored energy can be released in the next energy transfer cycle to raise the conversion efficiency. The circuit operations and design procedures are likewise examined thoroughly. Experimental results on a prototype inverter for driving a 100-A AC arc welding machine are recorded to validate the effectiveness of the presented scheme. Copyright © 2010 John Wiley & Sons, Ltd.

A CMOS voltage regulator for passive RFID tag ICs

Abstract: A low-power voltage regulator for passive RFID tag ICs is proposed in this paper. It consists of a self-biased mutually compensated voltage reference, a low dropout (LDO) voltage regulation circuit and a power-on-reset (POR) circuit. It is fabricated in a commercial 0.18−µm CMOS technology and applied to a passive UHF RFID tag IC. The total quiescent current is 700 nA under a 1.8-V supply. The output voltage of the regulator is 1.45 V with load capability of 50 µA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/∘C, respectively. A POR signal with width pulse of 150 ns is generated for the digital part in the tag IC. Copyright © 2010 John Wiley & Sons, Ltd.

Time-domain analysis of phase-noise and jitter in oscillators due to white and colored noise sources

Abstract: This paper presents an original time-domain analysis of the phase-diffusion process, which occurs in oscillators due to the presence of white and colored noise sources. It is shown that the method supplies realistic quantitative predictions of phase-noise and jitter and provides useful design-oriented closed-form expressions of such phenomena. Analytical expressions and numerical simulations are verified through measurements performed on a relaxation oscillator whose behavior is perturbed by externally controlled noise sources. Copyright © 2011 John Wiley & Sons, Ltd.

Low-noise, low-sensitivity, active-RC allpole filters using impedance tapering

Abstract: In this paper it is shown that active-RC filters whose sensitivity to component tolerances can be minimized by impedance tapering, will also have low output thermal noise It is shown that impedance tapering will also reduce output thermal noise in OTA-C filters Copyright © 2010 John Wiley & Sons, Ltd (This work was partially supported by the Ministry of Science, Education and Sports of Republic of Croatia)

A sub-1V supply CMOS voltage reference generator

Abstract: An integrated sub-1V voltage reference generator, designed in standard 90-nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p-n-p substrate vertical bipolar devices and a voltage-to-current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter-base voltage of the core p-n-p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail-to-rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/∘C in the range of − 40 and 125∘C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of − 36 and 125∘C. Copyright © 2011 John Wiley & Sons, Ltd.