Patent
Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function
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TLDR
In this article, the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit.Abstract:
Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.read more
Citations
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References
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Patent
Multi-bit-per-cell flash EEPROM memory with refresh
Hock C. So,Sau C. Wong +1 more
TL;DR: In this article, a multibit per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges correspond to forbidden zones indicating a data error.
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Method and apparatus for significantly improving the reliability of multilevel memory architecture
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Patent
Method and apparatus for performing error correction on data read from a multistate memory
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Patent
Data management for multi-bit-per-cell memories
Sau Ching Wong,Hock Chuen So +1 more
TL;DR: A multi-bit-per-cell memory can reduce the effect of defects and data errors by scrambling data bits before writing data as mentioned in this paper, which prevents storage of consecutive bits in the same memory cell.
Patent
Device and a method for storing data and corresponding error-correction information
TL;DR: In this article, the authors proposed a multi-level storage device including at least a first plurality of cells storing an identical first number (greater than one) of binary data, and a corresponding for second plurality for storing a second number of error check and correcting words equal to the first number.