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Patent

Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device

TLDR
In this paper, a method for readily forming a bump with a desired width, a semiconductor device and a method to make the same, a circuit board, and an electronic device is presented.
Abstract
The invention provides a method for readily forming a bump with a desired width, a semiconductor device and a method for making the same, a circuit board, and an electronic device. A method for forming a bump includes forming an opening in an insulating film which exposes at least a part of a pad, and forming the bump so as to be connected to the pad. A resist layer 20 defines a through hole which extends over at least a part of the pad in plan view. A metal layer is formed in the opening so as to connect to the exposed portion of the pad.

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Citations
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Patent

Low fabrication cost, fine pitch and high reliability solder bump

TL;DR: In this paper, a column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of a contact pad.
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Method of wire bonding over active area of a semiconductor circuit

TL;DR: In this paper, a method and structure for wire bond connections over active and/or passive devices and low-k dielectrics, formed on an Integrated Circuit die, is presented.
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Semiconductor device and method of manufacturing the same

TL;DR: In this article, a semiconductor device, including an electrode pad formed above the semiconductor layer, an insulating layer formed over the electrode pad and having an opening which exposes at least part of the electrodes, is described.
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Method of assembling chips

TL;DR: A method of assembling chips is described in this paper, where a first chip and a second chip are provided, and at least one conductive pillar is formed on the first chip.
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Reliable metal bumps on top of I/O pads after removal of test probe marks

TL;DR: In this paper, a method for the creation of metal bumps over surfaces of I/O pads is described, which can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which a contact pad has been deposited.
References
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Patent

Method of forming metal contact pads and terminals on semiconductor chips

TL;DR: In this article, a method of forming metal contact terminals of a determined size having an insulating substrate (17) with a metal land (18) formed thereon and a passivating layer (19) provided with an opening exposing a part of the metal land by forming intermediate metal contact pad (33') in the contact opening, applying and patterning a photoresist, delineating the intermediate metamodel using pattern (31) as an in-situ mask, depositing a lead-tin solder layer (34') over a metal mask to form a solder bump (
Patent

Method of building solder bumps

TL;DR: In this article, a method of forming a spheroid solder bump on an under-bump metallurgy is proposed, in which a contact pad on a substrate material is partially covered by a passivation layer upon the substrate material which is non-wettable by solder and in which the under bump metallomics covers the portions of the contact pad which are not covered by the passivated layer and overlaps from the contactpad to cover portions of a passivated surface.
Patent

Manufacture of semiconductor device

TL;DR: In this paper, a polyimide film is used as a protection film by removing a large step area at the end of the scribe line in order to complete the etching.
Patent

Semiconductor device with flip chip bonding pads and manufacture thereof

TL;DR: In this paper, a semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface and the other area being covered with a first insulating film.
Patent

Manufacture of semiconductor device

Kikkai Akira
TL;DR: In this article, the authors proposed a method to enable electrical selection of individual chips at the stage of a semiconductor wafer by a method wherein flip chip type semiconductor chip regions, where element electrodes are arranged in an array type, and the arrangement of extraction electrodes for selection use on the peripheral regions of the individual chips are simultaneously formed on the semiconductor Wafer.
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