Patent
Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer
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TLDR
In this paper, an electrical isolation mechanism is formed in a semiconductive body to separate islands of an upper zone of first type conductivity (N) in the body, and a path of first-type conductivity extending from the PN junction through another of the islands to its upper surface is created.Abstract:
In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.read more
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References
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Patent
Electrically programmable read-only memory stacked above a semiconductor substrate
TL;DR: In this article, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode mean and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layers; and outputs from the address decoding means respectively couple through the insulators to the select lines.
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Thin film memory device employing amorphous semiconductor materials
TL;DR: In this paper, a thin-film amorphous memory cell is proposed to minimize the surface area requirements for each memory array and increase the packing density of the memory array by using a tellurium-based chalcogenide material.
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Irreversible semiconductor switching element and semiconductor memory device utilizing the same
TL;DR: A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage as mentioned in this paper.
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PROM electrically written by solid phase epitaxy
TL;DR: In this article, a memory cell, having a doped amorphous silicon layer, is formed on a thin layer of silicon alloy which is on a single crystal silicon substrate.
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Reversibly programmable polycrystalline silicon memory element
TL;DR: A polycrystalline silicon memory element having an impurity concentration in the range of 10 17 to 10 20 atoms per cubic centimeter is reversibly switchable from a high to a low resistance state through a negative resistance region using a voltage above the threshold having a ramped trailing edge.