Patent
Method of manufacturing a semiconductor integrated circuit BI-MOS device
TLDR
In this article, a method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and a base layer of one conductivity type by a surrounding dielectric followed by removing the oxide film from emitter and collector electrode extending regions.Abstract:
A method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and a base layer of one conductivity type by a surrounding dielectric followed by removing the oxide film from emitter and collector electrode extending regions. A silicon film of a second conductivity type is formed by patterning and used to form an emitter layer and a collector extending layer by differing impurities from the silicon film. Patterning is then employed to form gate, emitter and collector electrodes. Finally, the mask for the silicon film is used to form a base electrode extending layer, a source layer and a drain layer of the first conductivity type and of high impurity density.read more
Citations
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Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size
TL;DR: In this paper, a high performance MOS transistor structure of either the N channel or P channel variety and a high-performance bipolar transistor structure was proposed. And a process is described which can make high performance CMOS and high performance bipolar devices on the same die.
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TL;DR: In this article, a self-aligned implant mask was used to mask the NPN transistor site during the implant of the base regions of the NMOS/FAMOS transistor.
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Method for fabricating bipolar-MOS devices
Tatsuya Deguchi,Fumitake Mieno +1 more
TL;DR: In this paper, a method for fabricating bipolar-MOS devices having n-, p-, and bipolar transistors, each fabricated in a respective silicon single crystal layer grown in openings formed in a field oxide layer covering a silicon substrate, is presented.
References
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Patent
Semiconductor device and method of manufacturing the device
TL;DR: In this paper, a semiconductor device having at least an insulated gate field effect transistor is described, which is a very advantageous method of manufacturing said structure in which the insulating pattern and the gate electrodes serve as masks.
Patent
MIS semiconductor device and method of manufacturing the same
TL;DR: In this article, a metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole and a poly-crystalline poly-poly-silicon film on the insulating material.
Patent
Epitaxial outdiffusion technique for integrated bipolar and field effect transistors
TL;DR: In this paper, an NPN transistor, a P channel and an N channel field effect transistor are formed in the same epitaxial layer on a monolithic semiconductor substrate.
Patent
Fabrication of complementary bipolar transistors and CMOS devices with poly gates
TL;DR: In this article, specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistor, and the last diffusion step for shallow P + and N + emitter regions and contact regions is performed without a separate diffusion cycle.
Patent
Method of manufacturing Si gate MOS integrated circuit
TL;DR: In this article, the gate oxide is removed and phosphorous is diffused into the exposed silicon substrate surfaces, leaving a thin layer of silicon nitride, which is then grown over the exposed polysilicon substrate surfaces.