Patent
Monolithic digital phaselock loop circuit having an expanded pull-in range
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TLDR
In this paper, a monolithic phaselock loop circuit is proposed for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by ±50% of the frequency of the reference clock.Abstract:
A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by ±50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.read more
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Patent
Self-calibrating phase-lock loop with auto-trim operations for selecting an appropriate oscillator operating curve
William B. Wilson,Un-Ku Moon +1 more
TL;DR: A phase-lock loop (PLL) has an oscillator having a plurality of operating curves, which are automatically trimmed to an appropriate oscillator operating curve for use during normal PLL operations as discussed by the authors.
Patent
Self-calibrating voltage-controlled oscillator for asynchronous phase applications
Un-Ku Moon,William B. Wilson +1 more
TL;DR: In this article, a phase-lock loop (PLL) auto-trim is used to select an appropriate oscillator operating curve for use during normal PLL operations, where the state machine uses different signals to determine whether the center frequency of each operating curve in the sequence is above or below the desired nominal operating frequency.
Patent
Lock detect circuit for detecting a lock condition in a phase locked loop and method therefor
TL;DR: In this article, a lock detect circuit (18) determines when a reference frequency and a feedback frequency are frequency locked using a reference counter (32) and feedback counter (36).
Patent
Wide range digital frequency detector
TL;DR: In this article, a wide band digital frequency detector is used to generate an oscillator clock signal based on a reference clock signal, which is then coupled with an up-down counter to control the oscillator frequency.
Patent
Low jitter phase locked loop having a sigma delta modulator and a method thereof
TL;DR: In this article, a phase-locked loop PLL has a current controlled oscillator, having an input resistance Rin, whose input resistance is proportional to a control current Idac sent to ICO.
References
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Patent
Interruptable voltage-controlled oscillator and phase-locked loop using same
TL;DR: In this article, a phase detector circuit is obtained by combining time-delay circuits and a voltage-controlled oscillator, which is assembled by connecting three ECL gates with controlled fall-times in a ring oscillator configuration.
Patent
Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
TL;DR: In this paper, a pair of variable frequency oscillators (VFO) are fabricated on the same integrated circuit chip so that corresponding components have substantially identical characteristics, and the output of the second VFO provides the local clock signal and can be varied further by a second correction signal.
Patent
Data tracking clock recovery system using digitally controlled oscillator
TL;DR: In this paper, a phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal, and the PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships.
Patent
PLL circuit with band width varying in accordance with the frequency of an input signal
TL;DR: In this paper, a PLL circuit comprises a phase comparator for inputting input and output clock signals and detecting a difference in phase between these both signals and outputting a signal based on the phase difference; a proportional circuit for converting the output signal to a signal processing circuit for performing predetermined data processing operations according to first and second operating states with respect to the data read operation, and an operational circuit having at least integral characteristics.
Patent
Circuit for detecting a lock of a phase locked loop
TL;DR: In this paper, a phase comparator and a waveform shaping circuit are connected to a multi-stage counter to generate phase difference signals when the phase difference signal indicates a phase difference exceeding a predetermined value.