MOS transistor and fabrication method thereof

TLDR: In this paper, a gate structure is provided for fabrication of MOS transistor, and the first and second spacers are then etched to expose a portion of the vertical sidewalls of the gate and adjacent to source/drain regions.

Abstract: A method for fabricating MOS transistor. The method includes the steps of providing a substrate with a gate structure thereon, and then forming first spacers on the sidewalls thereof. Thereafter, a first ion implantation is carried out using the gate structure and the first spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, second spacers are formed on the exterior sidewalls of the first spacers. Then, a second ion implantation is carried out using the gate structure, the first spacers and the second spacers as a mask to form source/drain regions in the substrate. The first and second spacers are then etched to expose a portion of the vertical sidewalls of the gate and a portion of the substrate adjacent to source/drain regions. The exposed top surfaces of the gate, the exposed portion of the vertical sidewalls of the gate and the exposed source/drain regions are then covered by silicide formed during silicidation. Finally, the remaining metal is removed and the formation of salicide (self-aligned silicide) is completed.