D
Dong-Suk Shin
Researcher at Samsung
Publications - 95
Citations - 1543
Dong-Suk Shin is an academic researcher from Samsung. The author has contributed to research in topics: Layer (electronics) & Semiconductor device. The author has an hindex of 19, co-authored 95 publications receiving 1529 citations. Previous affiliations of Dong-Suk Shin include Sungkyunkwan University.
Papers
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Proceedings ArticleDOI
High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability
Sung Dae Suk,Sung-young Lee,Sung-min Kim,Eun-Jung Yoon,Min-Sang Kim,Ming Li,Chang Woo Oh,Kyoung Hwan Yeo,Sung Hwan Kim,Dong-Suk Shin,Kwan-Heum Lee,Heungsik Park,Jeorig Nam Han,Choong-Hee Park,Jong-Bong Park,Dong-Won Kim,Donggun Park,Byung-Il Ryu +17 more
TL;DR: For the first time, a gate-all-around twin silicon nanowire transistor (TSNWFET) was successfully fabricated on bulk Si wafer using self-aligned damascene-gate process.
Patent
Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
Sung-young Lee,Dong-Suk Shin +1 more
TL;DR: In this paper, a field effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET is presented. But the method is limited to the case of single-input single-output (SIMO) devices.
Patent
Methods of fabricating a semiconductor device using a selective epitaxial growth technique
TL;DR: In this paper, a selective epitaxial growth technique is used to construct a semiconductor substrate with a bottom-surface recess, and a selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxially semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the substrate.
Patent
Field effect transistors having a strained silicon channel and methods of fabricating same
Sung-young Lee,Dong-Suk Shin +1 more
TL;DR: In this article, a channel layer on the sidewalls of a structure on a semiconductor substrate and having at least a portion of the channel layer strained in a direction that the sidewall of the structure extend from the substrate are provided is considered.
Patent
Method of fabricating CMOS transistor and CMOS transistor fabricated thereby
TL;DR: In this paper, a method for improving the performance of first and second conductivity type MOS transistors is proposed. But the method is limited to the case of a single-input single-output (SISO) MOS transistor.