Patent
Multi-bit flip-flops and scan chain circuits
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TLDR
In this paper, a multi-bit flip-flop operating as a master-slave flipflop may minimize power consumption occurring in a clock path through which the clock signal is transmitted.Abstract:
A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.read more
Citations
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Patent
Standby mode state retention logic circuits
TL;DR: In this paper, a retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well, and the circuit exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.
Patent
Integrated circuit with low power scan system
TL;DR: In this paper, an integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells with a master latch, a slave latch, and a multiplexer having first and second inputs respectively connected to the master and slave latch for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal.
Patent
Time borrowing flip-flop with clock gating scan multiplexer
TL;DR: In this paper, an apparatus consisting of a multiplexer which is gated by a clock, and a flip-flop coupled to the multiple-xer, is described, where the flip-Flop has a chain of at least four inverters one of which has an input to receive the clock.
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TL;DR: In this article, a memory includes a clock generator and a multiplexing latch circuit, which is configured to generate a first latching clock signal and a second latching signal.
Patent
Multi-bit flip-flop with soft error suppression
Alexander Ivanovich Kornilov,Victor Mikhailovich Mikhailov,Mikhail Yurievich Semenov,David R. Tipple +3 more
TL;DR: In this article, the authors propose a split clock path that routes different shared clock signals that control the timing of the latches to reduce the impact of soft errors on the clock signals.
References
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Patent
Apparatus and method for detecting the loss of a current transformer connection coupling a current differential relay to an element of a power system
TL;DR: In this article, an apparatus and method for detecting a loss of a current transformer connection coupling a relay to a power system element of a three-phase power system and providing a plurality of secondary current waveforms of the three phase power system to the relay is presented.
Patent
Data storage circuits using a low threshold voltage output enable circuit
TL;DR: In this paper, a data storage circuit (30) comprises a data input (12') for receiving a data voltage (D') and a data output (19') for providing an output voltage in response to the interim voltage at the node.
Patent
Data retention cell and data retention method based on clock-gating and feedback mechanism
TL;DR: In this paper, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal, and the output signal is furnished backward to an input control circuit.
Patent
Master slave flip-flop circuit functioning as edge trigger flip-flop
TL;DR: In this article, the connection of the first line and disconnection of the second line are performed to change the states of the master and slave latch circuits in response to a clock signal.
Patent
Flip flop circuit & same with scan function
Chung-hee Kim,Min-Su Kim +1 more
TL;DR: In this article, a pulse-based flip flop, which outputs a scan input signal and a data signal, was proposed to coordinate the operation of the flip-flop, and a latch unit was used to transfer the signal received from the multiplexer according to the pulse signal.