Patent
Multi-level amplitude signaling receiver
TLDR
In this article, a receiver circuit for multi-level amplitude signaling with at least three amplitude levels for each symbol period is described. But the receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit, and the peak detector is arranged to detect a peak voltage of the multilevel amplitude signal.Abstract:
One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.read more
Citations
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Patent
Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication
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Patent
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References
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Patent
Offset cancellation in a multi-level signaling system
TL;DR: In this paper, a threshold generating circuit combines a first control value and a second control value to generate the first threshold value and provide the first value to the sampling circuit, which is then used by the threshold generator.
Patent
Apparatus and method thereof for clock and data recovery of n-pam encoded signals using a conventional 2-pam cdr circuit
Yaron Slezak,Genady Veytsman +1 more
TL;DR: An interface circuit for enabling clock and data recovery (CDR) of N-level PAM modulated data streams using a 2-PAM CDR circuit is presented in this article.
Patent
Display, timing controller and column driver integrated circuit using clock embedded multi-level signaling
TL;DR: In this article, a display, a timing controller and a column driver integrated circuit using clock embedded multi-level signaling is described. But the present paper only relates to a display.
Patent
Circuit for multiplexing a plurality of signals on one transmission line between chips
TL;DR: In this paper, the authors proposed a method for the simultaneous transmission of three digital signals from one integrated circuit to another by using series resistors of predetermined values and then transmitted by one transmission line to the second integrated circuit chip.