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Patent

Multi-processor parallel computer architecture using a parallel machine with topology-based mappings of composite grid applications

Lorie M. Liebrock
TLDR
In this article, a parallelization process for complex-topology applications is based on an understanding of topology and includes two separate parts: i) an automatic, topology-based data distribution method and ii) a program transformation method.
Abstract: 
A parallelization process for complex-topology applications is based on an understanding of topology and includes two separate parts: i) an automatic, topology-based data distribution method and ii) a program transformation method. Together these methods eliminate the need for user determined data distribution specification in data layout languages such as High Performance Fortran. The topology-based data distribution method uses both problem and machine topology to determine a data-to-processor mapping for composite grid applications. The program transformation method incorporates statements in the user program to read and implement the data layout determined by the distribution method and to eliminate the need for user development and support of subroutine clones for data distribution.

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Patent

Method, system and computer program product for server selection, application placement and consolidation

Ramesh Baskaran, +5 more
TL;DR: In this article, a plurality of application profiles are obtained, for plurality of applications, and a recommended server configuration is generated for running the applications by formulating and solving a bin packing problem, where each of the at least two different kinds of servers is treated as an item, with an associated size, to be packed into the bins.
Patent

Flow of streaming data through multiple processing modules

Rafael S. Lisitsa, +3 more
TL;DR: Frame-based streaming data flows through a graph of multiple interconnected processing modules as discussed by the authors, which have a set of performance parameters whose values specify the sensitivity of each module to the selection of certain resources of a system.
Patent

Storage media data structure system and method

Clark Edward Lubbers, +1 more
TL;DR: In this article, a data storage architecture employing a plurality of data grids each comprising an array of equal capacity data storage blocks is proposed, where each data storage unit reflects a storage format such as a RAID level, and defines data storage units, mirror data blocks, and parity data blocks depending upon storage the format and can provide fault tolerance in the event of a domain failure.
Patent

Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules

Rafael S. Lisitsa, +3 more
TL;DR: In this paper, the data is carried in composite physically allocated frames having virtual subframes associated with different ones of the splitters, mixers, and other transform modules, and pipe control tables represent the structure of the pipes.
Patent

Determining a communication schedule between processors

Hideaki Komatsu, +1 more
TL;DR: In this paper, a communication graph is generated for distances between nodes from one through N-1 and each communication graph corresponds to a communication step of the inter-processor communication, and the edge of the communication graph means the interprocessor communication which is performed in a certain communication step.
References
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Patent

Dynamic multi-mode parallel processing array

Peter M. Kogge
TL;DR: In this article, a parallel RISC computer system is provided by a multimode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another.
Journal ArticleDOI

Generating Local Addresses and Communication Sets for Data-Parallel Programs

Siddhartha Chatterjee, +4 more
- 01 Apr 1995 - 
TL;DR: This work demonstrates a storage scheme for an array A affinely aligned to a template that is distributed across p processors with a cyclic(k) distribution that does not waste any storage and shows that the local memory access sequence of any processor for a computation involving the regular section A(?:h:s) is characterized by a finite state machine of at most k states.
Patent

Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements

Tobias M. Weinberg, +2 more
TL;DR: In this paper, a code generator and a scheduler are used to transform a source computer program to an assembly language program written in a non-standard instruction set, and the code generator eliminates the effects of pipeline delays when transforming the lowered intermediate representation to the assembly language programs.
Patent

Partitioning optimizations in an optimizing compiler

Joyce Marie Janczyn, +1 more
TL;DR: In this article, the number of entities in each subgraph which are relevant to each dimension of arrays used to represent data flow equations is determined, and the amount of memory required to contain the arrays is determined.
Patent

Method for the dynamic allocation of array sizes in a multiprocessor system

Tom MacDonald, +2 more
TL;DR: In this article, a method of setting array boundaries in order to simplify addressing across processor elements in a distributed memory system having global addressing is proposed, where each dimension of an array is examined to determine a lower bound, a declared upper bound and an implicit upper bound.