Patent
Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
Satyanarayana Nishtala,Zahir Ebrahim,William C. Van Loo,Paul N. Loewenstein,Sue K. Lee,Louis F. Coffin +5 more
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TLDR
In this paper, a multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller, each of which includes a master interface having master classes for sending memory transaction requests to the system controller.Abstract:Â
A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.read more
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Patent
Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
Zahir Ebrahim,Satyanarayana Nishtala,William C. Van Loo,Kevin Normoyle,Paul N. Loewenstein,Louis F. Coffin +5 more
TL;DR: In this article, the system controller includes transaction activation logic for activating each memory transaction request when it meets predefined activation criteria, and for blocking each said transaction request until the predefined activating criteria are met.
Patent
Apparatus and method for operating a peripheral device as either a master device or a slave device
TL;DR: In this paper, an apparatus capable of operating as either a master device or a slave device on a communication link such as a Universal Serial Bus (USB) is described, and a timer is used to determine the presence or absence of an active host controller.
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Method and apparatus for gigabit packet assignment for multithreaded packet processing
TL;DR: In this article, a network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface, is presented, where packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads.
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User-level dedicated interface for ip applications in a data packet switching and load balancing system
TL;DR: In this article, a buffer descriptor list defines the status of buffers provided in the kernel memory that are used for temporary storage of data packets transferred between the network application and the plurality of network interfaces via the network driver.
Patent
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
TL;DR: In this article, a speculative read request is issued to a home node before results of a cache coherence protocol are determined, and the home node initiates a read to memory to complete the read request.
References
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Patent
Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
Michael E. Flynn,Scott Arnold,Stephen J. Delahunt,Tryggve Fossum,Ricky C. Hetherington,David J. Webb +5 more
TL;DR: In this paper, a method for data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and correcting the data inconsistencies states so that the operation may be executed in a correct and consistent manner.
Patent
Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
TL;DR: In this article, the bus interface is coupled to the processor, the backup cache memory and to the bus in accordance with a SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items in the corresponding secondary cache memory having set VALID indicators.
Patent
Method and apparatus for filtering invalidate requests
TL;DR: In this paper, an apparatus which filters the number of invalidates to be propagated onto a private processor bus is provided. But it does not specify how to filter the invalidates.
Patent
System bus for multiprocessor computer system
TL;DR: In this article, the authors propose a system bus for multi-arm, multiprocessor computer systems with a main memory and localized buffer cache memories at each processor, where each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory.
Patent
Scheme for error handling in a computer system
TL;DR: In this paper, the authors present a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor.