D
David H. Albonesi
Researcher at Cornell University
Publications - 115
Citations - 7181
David H. Albonesi is an academic researcher from Cornell University. The author has contributed to research in topics: Microarchitecture & Cache. The author has an hindex of 37, co-authored 115 publications receiving 6909 citations. Previous affiliations of David H. Albonesi include University of Rochester & University of Massachusetts Amherst.
Papers
More filters
Proceedings ArticleDOI
Selective cache ways: on-demand cache resource allocation
TL;DR: In this paper, a tradeoff between performance and energy is made between a small performance degradation for energy savings, and the tradeoff can produce a significant reduction in cache energy dissipation.
Proceedings ArticleDOI
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
Greg Semeraro,Grigorios Magklis,Rajeev Balasubramonian,David H. Albonesi,Sandhya Dwarkadas,Michael L. Scott +5 more
TL;DR: An alternative approach is described, which is called a multiple clock domain (MCD) processor, in which the chip is divided into several clock domains, within which independent voltage and frequency scaling can be performed.
Proceedings ArticleDOI
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
TL;DR: This paper proposes a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis and demonstrates that a configurable L2/L3 cache hierarchy coupled with a conventional LI results in an average 43% reduction in memory hierarchy energy in addition to improved performance.
Journal ArticleDOI
On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions
Mikhail Haurylau,Guoqing Chen,Hui Chen,Jidong Zhang,Nicholas A. Nelson,David H. Albonesi,Eby G. Friedman,Philippe M. Fauchet +7 more
TL;DR: The International Technology Roadmap for Semiconductors (ITRS) is used as a reference to explore the requirements that silicon-based ICs must satisfy to successfully outperform copper electrical interconnects (IEs).
Proceedings ArticleDOI
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Nevin Kirman,Meyrem Kirman,Rajeev K. Dokania,Jose F. Martinez,Alyssa B. Apsel,Matthew A. Watkins,David H. Albonesi +6 more
TL;DR: This paper investigates the integration of CMOS-compatible optical technology to on-chip cache-coherent buses in future CMPs and yields a hierarchical opto-electrical system that exploits the advantages of optical technology while abiding by projected limitations.