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Patent

Phase locked loop for generating two disparate, variable frequency signals

TLDR
In this paper, a phase comparator is used to compare the reference signal with a feedback signal, which is then fed to a variable frequency divider circuit under control of a Σ/Δ converter to generate a lower frequency signal.
Abstract
A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a Σ/Δ converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.

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Citations
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Wireless communication system

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Frequency synthesizer and synthesis method for generating a multiband local oscillator signal

TL;DR: In this article, a phase-locked loop (PLL) frequency synthesizer was used to produce a local oscillator signal for a superheterodyne transmitter for operation at a first and a second RF frequency band that are disparate.
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Ratiometric clock systems for integrated receivers and associated methods

TL;DR: In this paper, a ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry.
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Systems and methods for providing off-line backup of a programmable device's configuration data to users of programmable devices at a service location

TL;DR: In this article, the authors present a system for providing support services to users of programmable devices, which involves the steps of: receiving user-specific data associated with one of the programmable device and the corresponding user, storing the userspecific data, configuring the replacement device based on the user-specified data associated to the device and its corresponding users, and receiving notification that a replacement device is needed by the user.
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Local oscillator apparatus for radio frequency communication systems

TL;DR: In this article, a local oscillator for radio frequency communication systems is described, which includes a regenerative modulator comprising a pair of frequency dividers and a single side band mixer.
References
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Patent

Multiple-modulator fractional-n divider

TL;DR: In this paper, a fractional-N type frequency synthesizer includes a frequency divider having a selectable integer divide number which is periodically temporarily altered to provide an average rational divide number for the frequency dividers.
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Frequency synthesizers having dividing ratio controlled by sigma-delta modulator

TL;DR: In this paper, a variable modulus divider is used to divide the output signal to provide the phase control signal, whose frequency varies in dependence upon a ratio control signal derived by a second or higher order sigma-delta modulator in response to a frequency control signal.
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Frequency synthesizer with fractional division ratio and jitter compensation

TL;DR: In this article, a frequency synthesizer with good resolution is obtained by a unity increase of the dividing ratio for a controlled proportion of the reference frequency cycles thus giving a fractional dividing ratio.
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Heterodyne radio receiver with plural variable frequency local oscillator signals

TL;DR: In this article, a satellite navigation receiver uses common dual-conversion superheterodyne and frequency synthesizer circuitry for receiving signals from both the GPS and the GLONASS satellite navigation systems.
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Linear low noise phase-frequency detector

TL;DR: In this paper, a phase-frequency detector (110) includes an output stage (300) and a control stage (200), which are coupled to a charge pump output node (111).