Patent
Power on reset circuit
James J. Remedi,Alan K. Peterson +1 more
TLDR
In this paper, a CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power, including a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt.Abstract:
A CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power The circuit includes a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt A capacitor is connected to the positive power supply terminal to avoid having a narrow output pulse when the power supply rises at a low rate An output buffer/inverter can be used to provide a better output pulse and to provide a desired output polarityread more
Citations
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Patent
Power supply and power enable circuit for an RF/ID transponder
TL;DR: In this paper, a power supply self-contained within a portable RF/ID transponder includes a full wave rectifier having an input for receiving an antenna signal and outputs for providing power supply and ground voltages, wherein the power supply voltage has a time varying voltage waveform corresponding to the electric field generated by a reader/controller.
Patent
Low current power-on reset circuit
TL;DR: In this article, a power-on reset circuit responds to a power decrease of very short duration by using a delay circuit having a high threshold inverter which reliably detects a voltage as high as a standard threshold voltage as a low voltage when the power supply voltage again begins to increase.
Patent
Power up detection circuit
TL;DR: In this paper, a power up detection signal for use in, and being integrated onto the same semiconductor substrate as a dynamic memory device is disclosed, where a first node and a circuit to promote a low voltage on the first node when a voltage obtained from a supply voltage applied to the dynamic memory is below a predetermined level.
Patent
Enhanced power-on-reset/low voltage detection circuit
TL;DR: In this paper, a comprehensive power-on-reset (POR) and low voltage detection circuit combines a Power Supply Voltage Level Detection (PSVLD) circuit with an Enhanced Retriggering (ER) circuit.
Patent
CMOS power-on detection circuit
TL;DR: In this paper, a CMOS power on detection circuit is described, which includes pairs of complementary MOS transistors being connected in series between two supply lines, each pair of transistors includes a long and a short channel transistor.
References
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Patent
MOS power-on reset circuit
TL;DR: In this paper, an automatic power-on reset circuit adapted for use on complementary MOS integrated circuit semiconductor dies is provided, which includes a voltage reference stage followed by an amplifier stage.
Patent
Voltage reference and voltage level sensing circuit
TL;DR: In this paper, the sum of threshold voltages of two transistors of different conductivity type is employed as a reference level in voltage sensing and other circuits, where a first transistor connected as a diode and its current source are connected in series between a pair of terminals to which a voltage to be sensed is applied.
Patent
Complementary FET pulse level converter
Lane Ralph D,Manning Richard C +1 more
TL;DR: In this article, an interfacing circuit for restoring voltage pulses to a desired fixed level is presented, which is particularly adapted to CMOS technology and includes features which result in rapid output rise and fall times, latching of the output voltage level, and isolation of the input following transition of input voltage between its respective final levels.