Patent
Programmable logic and driver circuits
TLDR
In this paper, an output driver circuit is described which can be programmed by the user into tri-state or open-collector configurations, depending on the needs of the user.Abstract:
An output driver circuit is described which can be programmed by the user into tri-state or open-collector configurations, depending on the needs of the user The driver circuit comprises a pair of a first pull-up and a pull-down FET transistor The source of the pull-up transistor and drain of the pull-down transistor are both connected to the output of the driver The gates of the pair of transistors are controlled by an input signal and its complement The driver further includes a second pull-up FET whose source is connected to the output of the driver The channel width to channel length ratio of the second pull-up transistor is at least about an order of magnitude greater than that of the first pull-up transistor The driver further includes a control means responsive to the input signal for applying a second signal to the gate of the second pull-up transistor for programming the driver into tri-state or open-collector modes The driver circuit may be controlled by the output of an OR gate in an AND-OR array in a FPLA or PAL device The driver is programmable by programming the AND gate or OR gate array and applying selected input signals to the AND gate array; the driver can also be programmed permanently into the tri-state or open-collector moderead more
Citations
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References
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Patent
Programmable array logic circuit
John M. Birkner,Hua-Thye Chua +1 more
TL;DR: In this article, the outputs from a field programmable AND gate array are connected, non-programmably, to specified OR gates for greater architectural and operational flexibility, registered outputs, internal feedback, input/output pin interchangeability, and means for allowing performance of arithmetical, as well as logic, operations, are provided.
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TL;DR: In this article, a voltage compatible circuit for providing TTL and CMOS level inputs and outputs is provided, where an input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal.
Patent
Programmable output buffer
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Logic circuit having a selectable output mode
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Patent
Totem pole/open collector selectable output circuit
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