Patent
Pulsed state retention power gating flip-flop
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TLDR
In this paper, a flip-flop includes a functional latch and a retention latch, and the retention latch is selectively coupled to the functional latch to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the powerdown mode is entered.Abstract:
A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.read more
Citations
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References
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Patent
Low standby power using shadow storage
Lawrence T. Clark,Franco Ricci +1 more
TL;DR: An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses may be used to generate data values that may be stored by the transistors having the thicker gate-oxides.
Patent
Retention register with normal functionality independent of retention power supply
TL;DR: In this paper, a state retention register for low-power standby modes of digital IC operation is provided, where a differential circuit (M 1 -M 3 ) is used to load the shadow latch from the normal functional latch.
Patent
High speed pulse based flip-flop with a scan function and a data retention function
TL;DR: In this article, a multi-threshold CMOS (MTCMOS) flip-flop is proposed for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal.
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Digital storage element architecture comprising integrated multiplexer and reset functionality
TL;DR: In this article, a digital storage element comprises a master transparent latch coupled to a slave transparent latch and comprising dedicated functional and scan data output ports, where the first and second clock signals are non-overlapping.
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Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop
TL;DR: In this paper, a control signal generator, latch circuit, flip-flop and method for controlling operations in the flipflop are configured so as to efficiently perform latching and scanning operations.