Patent
Reconfigurable dual processor system
Thomas Patrick Bishop,Jonas Butvila,David John Fitch,Robert Carl Hansen,David Anthony Schmitt,Grover Timothy Surratt +5 more
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In this article, a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks.Abstract:Â
A is a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode (10) in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks. The system automatically changes modes in response to requests such as manual and program control and certain system fault conditions. In diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one processor (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operaton (3-6). In two of these states (3,4) one processor is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stoped execution. In the other two of these states (5,6) one processor is active while the other processor is out of service and cannot take up task execution without being initialized. The system 100 makes transitions between the various states in response to requests. Except for transitions of an active processor to an out-of-service condition, the state transitions are transparent to tasks other than fault recovery programs and, upon a fault condition, the faulted program.read more
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Double redundant processor
TL;DR: In this paper, a double redundant processor including first and second master processors for processing data, control and address signals in a data processing system is described. But the first master processor is in an active state for processing the signals and the second master processor, in a standby state, is in a non-active state.
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Balancing data-processing work loads
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Peripheral unit controller.
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TL;DR: In this article, an automatic fault recovery system for a multiple processor control complex of a telecommunications switching system is described, which deals with the occurrence of soft faults and localizes the effect of errors, with the goal of minimizing disruption of calls through the switching system.