Patent
RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output
Sam M. Daniel,Brian K. Short +1 more
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TLDR
The RICS microprocessor architecture as discussed by the authors provides a plurality of data registers and instruction registers each having a multi-bit extension for extending the width of the data and instruction words processed therethrough, which allows full precision computation for the data words requiring the tag field to identify the data type thereof while retaining full precision compatibility for data words not needing tag field identifiers.Abstract:
A RICS microprocessor architecture is provided with a plurality of data registers and instruction registers each having a multi-bit extension for extending the width of the data and instruction words processed therethrough. A first plurality of bits within a tag field of the multi-bit extension are reserved for identifying the data type of the data words while a second plurality of bits provide instruction dependent control. The multi-bit extension allows full precision computation for the data words requiring the tag field to identify the data type thereof while retaining full precision compatibility for data words not needing tag field identifiers. At least two bits of the first plurality of bits in tag field are reserved for identifying one of several primary categories of data types and at least two bits identify one of several subtype categories within each of the plurality of primary categories. An extended set of machine instructions is also provided for efficient usage of the multi-bit extension appended to the data and instruction registers.read more
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High performance, superscalar-based computer system with out-of-order instruction execution
Le Trong Nguyen,Derek J. Lentz,Yoshiyuki Miyayama,Sanjiv Garg,Yasuaki Hagiwara,Johannes Wang,Te-Li Lau,Sze-Shun Wang,Quang H. Trang +8 more
TL;DR: In this paper, a superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput is presented, where the data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
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References
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Patent
Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
TL;DR: In this article, a VLSI processor of the reduced instruction set computer (RISC) type is enhanced by executing two instructions simultaneously in the two execution units of the processor.
Patent
Tag Data processing apparatus for a data flow computer
Hajime Asano,Hiroaki Terada,Katsuhiko Asada,Nishikawa Hiroaki,Shimizu Masahisa,Hiroki Miura,Kenji Shima,Shinji Komori,Souichi Miyata,Satoshi Matsumoto +9 more
TL;DR: In this paper, a tag data processing apparatus was described for use in a data flow computer utilizing a tagged token scheme, where a tag adding process and tag restoring process were executed by using pipeline registers, a queue memory and simple control circuit.
Patent
Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
TL;DR: In this article, the authors propose a simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution, which is particularly suited to reduced instruction-set computers (RISCs).
Patent
Arithmetic logic unit
TL;DR: In this paper, a suppressing circuit is used to suppress unnecessary bytes other than operand bytes and all of the bytes of one of the operands when the one operand has been exhausted.
Patent
Tagged pointer handling apparatus
Glen Robert Mitchell,Kempke William George,Eugene Reese Jones,Houdek Merle Edward,James Gregory Ranweiler +4 more
TL;DR: Tagged pointer handling as mentioned in this paper allows the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions.