Patent
Semi-conductor floating gate memory cell with write and erase electrodes
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TLDR
In this paper, a floating-gate storage cell consisting of an n-channel field-effect transistor whose potentially floating gate electrode comprises a first electrode part which, for effecting the tunnel injections of electrons into the gate electrode (1), is coupled capacitively to a writing electrode (4), as well as a second electrode part of polycrystalline silicon which, during the erasing operation, is coupled to an erasing electrode (3), characterized in that the coupling capacitance of said programming electrode (2) towards said gate electrode(1) is greater than thatAbstract:
1. Floating-gate storage cell consisting of an n-channel field-effect transistor whose potentially floating gate electrode comprises a first electrode part which, for effecting the tunnel injections of electrons into the gate electrode (1), is coupled capacitively to a writing electrode (4), as well as a second electrode part of polycrystalline silicon which, for effecting the tunnel emissions of electrons from said gate electrode (1) during the erasing operation, is coupled capacitively to an erasing electrode (3), characterized in that moreover said gate electrode (1) is coupled capacitively to a programming electrode (2), that said writing electrode (4) is connected directly in a barrier-free contact to the drain zone (5) of the field-effect transistor, and that the coupling capacitance of said programming electrode (2) towards said gate electrode (1) is greater than that of said writing electrode (4) towards said gate electrode (1) and greater than that of said erasing electode (3) towards said gate electrode (1).read more
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Patent
Non-volatile semiconductor memory
Yukihiro c,o Seiko Instr. Electronics Ltd Imura,Masaaki c,o Seiko Instr. Electronics Ltd Kamiya,Katsuyuki Seiko Instr. Takahashi +4 more
TL;DR: In this paper, a non-volatile semiconductor memory comprises source and drain regions, a gate insulator film, a floating gate electrode, and a control gate above the floating gate.
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EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit
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TL;DR: In this article, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure, and a control circuit coupled with the memory cell.
References
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Patent
High density floating gate electrically programmable ROM
TL;DR: An N-channel double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines as mentioned in this paper.
Patent
Electrically alterable floating gate semiconductor memory device with series enhancement transistor
TL;DR: An N-channel double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by two address lines as mentioned in this paper.
Patent
Storage FET with insulated storage gate - has insulated control gate and is fitted with high internal capacitance between gates
TL;DR: In this article, a storage FET is fitted with an insulated floating storage gate (G1) and an insulated control gate(G2) and it has a characteristic internal capacitance (C2) between the storage gate and the control gate.