Journal ArticleDOI
Sequential Program Prefetching in Memory Hierarchies
TLDR
It is shown that prefetching all memory references in very fast computers can increase the effective CPU speed by 10 to 25 percent.Abstract:
Memory transfers due to a cache miss are costly. Prefetching all memory references in very fast computers can increase the effective CPU speed by 10 to 25 percent.read more
Citations
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Journal ArticleDOI
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
Proceedings ArticleDOI
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
TL;DR: In this article, a hardware technique to improve the performance of caches is presented, where a small fully-associative cache between a cache and its refill path is used to place prefetched data and not in the cache.
Proceedings ArticleDOI
Lockup-free instruction fetch/prefetch cache organization
TL;DR: A cache organization is presented that essentially eliminates a penalty on subsequent cache references following a cache miss and has been incorporated in a cache/memory interface subsystem design, and the design has been implemented and prototyped.
Proceedings ArticleDOI
Trace processors
TL;DR: The results affirm that significant instruction-level parallelism can be exploited in integer programs (2 to 6 instructions per cycle) and quantify the value of successively doubling the number of distributed elements.
Journal ArticleDOI
A study of integrated prefetching and caching strategies
TL;DR: It is proved that the performance of the conservative approach is within a factor of two of optimal and that theperformance of the aggressive strategy is a factor significantly less than twice that of the optimal case.
References
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Journal ArticleDOI
Evaluation techniques for storage hierarchies
TL;DR: A new and efficient method of determining, in one pass of an address trace, performance measures for a large class of demand-paged, multilevel storage systems utilizing a variety of mapping schemes and replacement algorithms.
Journal ArticleDOI
The IBM System/360 model 91: machine philosophy and instruction-handling
TL;DR: It is shown that history recording (the retention of complete instruction loops in the CPU) reduces the need to exercise storage, and that sophisticated employment of buffering techniques has reducedt he effective access time.
Journal ArticleDOI
Sequentiality and prefetching in database systems
TL;DR: It is found that anticipatory fetching of data can lead to significant improvements in system operation and is shown how to determine optimal block sizes.
Journal ArticleDOI
A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory
TL;DR: It is suggested that as electronically accessed third-level memories composed of electron-beam tubes, magnetic bubbles, or charge-coupled devices become available, algorithms currently used only for cache paging will be applied to main memory, for the same reasons of efficiency, implementation ease, and cost.