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Silicon Microfabrication Technologies for Nano-Satellite Applications
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R. J. Shul, S. H. Kravitz, T. R. Christenson? C. G. Willison, and T. E. Zipperian’
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Abstract
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Silicon (Si) has a strength to density ratio of 3.0(aY/6=(6.8Gpa/2.3g/cc)), an
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order-of-magnitude higher than titanium, aluminum, or stainless steel. Silicon also
demonstrates favorable thermal, optical, and electrical properties making it ideal for
use as a structural foundation for autonomous, mesoscopic systems such as
nanosatellites. Using Si substrates, a structure that can simultaneously act as a
thermal management system, a radiation shield, an optical material, a package, and a
semiconductor substrate can be realized.
Introduction
Recently, several semiconductor fabrication processes have been developed
to en~ble the use of Si substrates as structural foundation for autonomous,
mesoscopic systems. Perhaps the most important development has been a deep
reactive ion etch (DRIE) process which has revolutionized the concept and
implementation of mixed technology integration. Using the. DRIE process, a Si
substrate may be etched to specific depths with highly controlled lateral dimensions.
This allows accurate alignment of dissimilar components and materials to one
another and accurate wafer-to-wafer alignment. Utilizing on-chip microelectronic
and mechanical structures, this technology will enable fabrication of a self-
contained, highly versatile, integrated rnicrosystem that will minimize volume,
weight, and power requirements.
DRIE also enables the pursuit of a collection of
advanced packaging capabilities to address the need for complex rnicrosystems that
combine multiple materials and functions in a single package or assembly.
Discussion and Results
Pattern transfer into Si has been very successful by both wet chemical and
plasma etch techniques. However, the fabrication of deep, high-aspect ratio Si
structures has been limited due to low etch selectivity to photoresist masks, slow
etch rates, or poor lateral dimensional control. The recent development of the DRIE
Si etch process has resulted in anisotropic profiles at room temperature, etch rates>
3.0 prnhnin, aspect ratios >30:1, and good dimensional control. Additionally, DRIE
has shown etch selectivities of Si to photoresist >75:1 thereby eliminating the use of
hard etch masks for features deeper than 100 pm.
The DRIE process (patented by Robert Bosch GmbH) [1] relies on an
iterative inductively coupled plasma (ICP) deposition/etch cycle in which a polymer
‘ Sandia National Laboratories, Albuquerque, New Mexico 87185-0603
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DISCLAIMER
This repofl was prepared as an account of work sponsored
by an agency of the United States Government. Neither the
United States Government nor any agency thereof, nor any
of their employees, make any warranty, express or implied,
or assumes any legal liability or responsibility for the
accuracy, completeness, or usefulness of any information,
apparatus, product, or process disclosed, or represents that
its use would not infringe privately owned rights. Reference
herein to any specific commercial product, process, or
service by trade name, trademark, manufacturer, or
otherwise does not necessarily constitute or imply its
endorsement, recommendation, or favoring by the United
States Government or any agency thereof. The views and
opinions of authors expressed herein do not necessarily
state or reflect those of the United States Government or
any agency thereof.
DISCLAIMER
Portions of this document may be illegible
in electronic image products. Images are
produced from the best available original
document.
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etch inhibitor is conformably deposited over the wafer during the deposition cycle.
The polymer deposits over the resist mask, the exposed Si field, and along the
sidewall. During the ensuing etch cycle, the polymer film is preferentially sputtered
from the Si trenches and the top of the resist mask due to the acceleration of ions
(formed in the ICP plasma) perpendicular to the surface of the wafer. Provided the
ion scattering is relatively low, the polymer film on the sidewall is removed at a
much slower rate, thus minimizing lateral etching of the Si. Before the sidewall
polymer is completely removed, the deposition step is repeated and the cycle
continues until the desired etch depth is obtained.
Through-wafer plated vias for electrical interconnects are used in many
integrated rnicrosystems including nano-satellites. Recently, a robust electroplated
via technology for through-wafer interconnects has been developed using several
microfabrication processes. These processes included Si DRIE to form the through-
wafer via holes, steam oxidation to isolate the metal via plugs from the silicon
substrate, and electroplating to form the metal plugs. As shown in Figure la, 100
pm wide vias are formed in
-425 Lm thick Si using the DRIE process. Electrical
isolation of the silicon substrate from the metal via plugs is achieved using steam
oxidation. For high aspect ratio (>1: 1) vias, neither LPCVD nor PECVD deposition
processes will adequately isolate the via.
These processes are limited by the
diffusi6n of large molecules into the via and the diffusion of reaction products out of
the via. As a result, the deposited film thickness decreases with depth into the via.
However, steam oxidation of silicon can completely insulate vias by
growing the oxide in place, rather than depositing films onto exposed surfaces. In
this case, only water and oxygen molecules need to enter the via while hydrogen is
the only reaction product. The oxide grown in the vias is uniform throughout the
entire depth. The rate of oxidation of films over 1000 ~ thick is limited by
diffusion of water and oxygen through the existing oxide film. At one atmosphere
pressure, the practical limit for oxide growth is about 2 pm at 1200”C. h high
pressure (25 atmospheres) oxidation systems, it is possible to grow thicker films in
shorter times or to oxidize at temperatures as low as 500°C. The breakdown voltage
for steam oxidized films is about 100 volts per pm film thickness.
Following oxidation, the vias are electroplated using the following process.
A copper substrate is coated with polymethylmethacrylate (PMMA) photoresist and
solvent bonded to the Si wafer. The PMMA is removed in the via locations with a
deep ultraviolet (DUV) blanket exposure and development cycle using the oxidized
silicon wafer as a stencil mask. The vias are then electroformed using an electrolytic
nickel deposition.
Finally the copper plating fixture is completely removed in a
simple wet etch process. Plated vias Me shown in Figure lb for 100 pm wide vias.
A series of plated vias were tested electrically and determined to be isolated from
the Si wafer. A similar fabrication sequence for copper and gold vias is also
possible, as well as for nickel-iron (Permalloy) to allow the incorporation of through
wafer magnetic fl,uxpaths.
Another fabrication process required for integrated Microsystems is wafer
bonding. There are many device applications that can benefit from joining two
silicon wafers or a silicon and Pyrex wafer. These seals could be hermetic, which
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(a)
Figure 1. SEM micrographs of 100pm
process and b) Ni electroplated.
(b)
diameter vias a) etched using the DRIE
allows silicon to serve as a packaging medium as well as a device substrate. If two
or more substrates can be accurately aligned before sealing, the possibility for
ma.khg inexpensive and sophisticated devices from divergent technologies exists.
After wafer bonding occurs, the resultant sealed devices can be diced into individual
packages.
DRIE provides a process which enables accurate alignment of wafers as well
as precision die-to-wafer alignment for advanced packaging technologies.
A Si
substrate can be etched ~o multiple, specific depths while retaining accurately
controlled dimensions in the mask plane.
This permits accurate alignment of
discrete components to one another with alignment tolerances c 5 pm. In Figure 2,
the DRIE process was used to accurately align two Si samples to one another. A
130 ym wide pin was DRIE etched in the top Si wafer while a 132 pm wide well
was DRIE etched in the bottom Si wafer. The pins and wells were aligned and then
attached using a UV curing adhesive to tolerances of <5 pm on pieces - 10 cmz.
Using a slightly different pattern, pieces as large as % of a 3 inch Si wafer have been
slimed to tolerances of-25 um.
(i!) (b)
Figure 2. Schematic (a) and (b) SEM micrograph or DRIE etched Si pins and wells
for precision alignment for advanced packaging technologies.
Wafers can then be bonded together using a number of different techniques.
Commercially available
alignment accuracies of
wafer alignment/bonding systems are available with
& 2 pm. These machines can heat to 600”C, and apply
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