Patent
Stress isolating signal path for integrated circuits
TLDR
In this article, a stress isolating signal path with one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided.Abstract:
A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.read more
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Patent
Flip chip package and method of making
TL;DR: In this paper, a portion of a semiconductor die is rigidly flip chip bonded to a conductive base plate and a portion is bonded to flexible dielectric material to take advantage of the benefits of flip chip packaging while at the same time allowing for heat to be dissipated and for differential thermal expansion to be relieved.
Patent
Fabrication of deformable leads of microelectronic elements
TL;DR: In this paper, an element such as a semiconductor wafer or other body is provided with leads by applying a sacrificial layer over the front surface of the body, depositing leads onto the sacrificial layers so that the leads are connected to contact pads on the body and removing the sacrificing layer from beneath the leads.
Patent
Inter-chip communication
TL;DR: A quilt packaging system for microchip, a method for making such a quilt packing system, and microchips that may be used in a such an approach are described in this paper.
Patent
Test fixtures for C4 solder-bump technology
TL;DR: In this article, a two-level metal connector with only one via level accommodates motion due to thermal expansion and manufacturing tolerances by decoupling vertical and lateral freedom of motions.
Patent
Fabrication of semiconductor dies with micro-pins and structures produced therewith
TL;DR: In this article, a method for forming a semiconductor die, comprising forming a trench in a surface of the die, filing the trench with a sacrificial material, patterning the die to form a series of channels extending substantially perpendicularly to the trench, depositing a conductive material in the channels, and removing at least a portion of the sacrificial materials; and removing portions of a die under the trench so as to separate a portion from the trench from a portion on another side of the trench.
References
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Patent
High performance interconnect system for an integrated circuit
TL;DR: In this paper, a semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnect, except at electrical contact points.
Patent
Hybrid integrated circuit package structure
Matsuzaki Toshio,Hiroaki Toshima +1 more
TL;DR: In this paper, a hybrid integrated circuit including a circuit substrate on which at least one of an active and passive semiconductor element is formed, a lead frame having a plurality of leads and a support plate with an opening formed therein, and supporting the circuit substrate thereon, is presented.
Patent
Low-cost high-performance semiconductor chip package
TL;DR: In this article, a low-cost high-performance semiconductor chip package enabling a direct chip to printed circuit board connection comprises a semiconductor Chip (42) having a front surface and a back surface.
Patent
Encapsulated electrical component with planar terminals
TL;DR: A PACKAGED ELECTRICAL COMPONENT has STRAIN SENSITIVE ELEMENTS MOUNTED on STRAin ABSORBING PORTions of TERMINALs that are LOCATED in an ENCAPSULATION WHICH MAINTAINS the TERMINATED ELEMENTS of the Component in a COMMON PLANE at a surface of the ENCAPE as discussed by the authors.
Patent
Direct bond circuit assembly with crimped lead frame
TL;DR: An electric circuit assembly as discussed by the authors includes a ceramic substrate (14), a copper lead frame (20), having pad portions (22, 24, 26) directly bonded on the substrate, crimped portions (28, 30, 32) extending from the pad portions in a humped configuration above the substrate.