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Synchronous Oscillator Using High Speed Emitter Couple Logic (ECL) Inverters
B. Chakraborty,R. R. Pal +1 more
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TLDR
In this paper, a synchronous oscillator using a high speed low voltage Emitter Coupled Logic (ECL) inverter was presented, and a maximum improvement (increase) of locking range was obtained from circuit simulation as well as from practical circuit, using discrete components.Abstract:
This paper presents a synchronous oscillator using a high speed low voltage Emitter Coupled Logic (ECL) inverter. Using the positive feedback the locking range increases, compared to the oscillator without any positive feedback. A maximum improvement (increase) of locking range of around 172% was obtained from circuit simulation as well as from practical circuit, using discrete components. Here the supply voltage requirement is 2.1 volts.read more
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Synchronous communications
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R.D. Huntoon,A. Weiss +1 more
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TL;DR: The authors present the theory and experimental characterization of SOs in terms of selectivity, noise rejection, carrier-to-noise improvement, tracking range, and acquisition time.
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A Frequency-Dividing Locked-in Oscillator Frequency-Modulation Receiver
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