Patent
Sysplex shared data coherency method
David A. Elko,Jeffrey A. Frey,John Franklin Isenberg,Chandrasekaran Mohan,Inderpal S. Narang,Jeffrey M. Nick,Jimmy Paul Strickland,Michael D. Swanson +7 more
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TLDR
In this article, a method for controlling coherence of data elements sharable among a plurality of independently-operating central processing complexes (CPCs) in a multi-system complex (called a parallel sysplex) which contains sysplex DASDds (direct access storage devices) and a high-speed SES (shared electronic storage) facility is presented.Citations
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Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system
Daniel Weinreb,Sam J. Haradhvala +1 more
TL;DR: In this article, an apparatus and method for virtual memory mapping and transaction management in an object-oriented database system having permanent storage for storing data in at least one database, at least a cache memory for temporarily storing data, and a processing unit which runs application programs which request data using virtual addresses.
Patent
Software partitioned multi-processor system with flexible resource sharing levels
TL;DR: In this article, a configuration tree is used to partition a single multiprocessor into multiple partitions, each running a distinct copy, or instance, of an operating system, each of the partitions has access to its own physical resources plus resources designated as shared.
Patent
Method and apparatus for virtual resource handling in a multi-processor computer system
TL;DR: In this paper, a single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system.
Patent
Database indexing method and apparatus
TL;DR: In this article, a database indexing method and apparatus is described, which includes an index structure for indexing a plurality of objects that are logically divided into fine slices of 8,000 records (22) each, and the fine slices are grouped into coarse slices of 4,000 fine slices each.
Patent
Method and apparatus for dynamically sharing memory in a multiprocessor system
TL;DR: In this article, the authors describe a system where multiple instances of operating systems execute cooperatively in a single multiprocessor computer where all processors and resources are electrically connected together.
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Patent
Method for managing database recovery from failure of a shared store in a system including a plurality of transaction-based systems of the write-ahead logging type
TL;DR: In this article, the recovery of a database from failure of a shared store is bounded by determination of a recovery boundary which, when applied to the union of database system transaction logs, establishes a point in front of which are found log records of modifications to pages which were in the shared store when it failed.
Patent
Method for lock management, page coherency, and asynchronous writing of changed pages to shared external store in a distributed computing system
TL;DR: In this paper, the authors propose a method for increasing throughput of N-way central electronic complexes concurrently executing processes to selectively lockable data resources while maintaining coherency among replicates of the information state of any accessed resource.
Patent
Method and means for the sharing of data resources in a multiprocessing, multiprogramming environment
TL;DR: In this paper, each complex of a pair includes a resource lock manager (IRLM) which maintains the hold and wait locks for applications executing on the complex and selected wait locks of the other complex.
Patent
Multiprocessing system including a shared cache
TL;DR: In this article, the authors propose a control system for interlocking processors in a multiprocessing organization where each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors.
Patent
Shared two level cache including apparatus for maintaining storage consistency
TL;DR: In this paper, a multilevel cache buffer for a multiprocessor system is described, where each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors.