Patent
Systems and methods for error injection in data storage systems
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TLDR
In this article, the authors describe a solid-state storage system that can be configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory.Abstract:
Embodiments of the solid-state storage system provided herein are configured to perform improved mechanisms for testing of error recovery of solid state storage devices. In some embodiments, the system is configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory. Injected errors include corruption of data stored in the non-volatile memory, deliberate failure to execute storage operations, and errors injected into communication protocols used between various elements of the device. In some embodiments, injected errors can include direct errors that trigger an immediate execution of error recovery mechanisms and delayed errors that trigger execution of error recovery mechanisms at a later time. Error recovery mechanisms can be tested in an efficient, reliable, and deterministic manner to help ensure effective operation of storage devices. The integrity of non-volatile memory can also be tested.read more
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References
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Patent
Command queuing smart storage transfer manager for striping data to raw-NAND flash modules
TL;DR: In this article, a flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller, where data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager.
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Storage subsystem capable of adjusting ecc settings based on monitored conditions
Mark S. Diggs,David E. Merry +1 more
TL;DR: In this article, a storage subsystem monitors one or more conditions related to the probability of a data error occurring, and adjusts an error correction setting, and thus the quantity of ECC data used to protect data received from a host system.
Patent
Hybrid non-volatile memory system
TL;DR: In this paper, a hybrid non-volatile memory system is presented that uses nonvolatile memories based on two or more different NVM technologies in order to exploit the relative advantages of each NVM technology with respect to the others.
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Systems and methods for measuring the useful life of solid-state storage devices
TL;DR: A non-volatile solid-state storage subsystem, such as a nonvolatile memory device, maintains usage statistics reflective of the wear state, and thus the remaining useful life, of the subsystem's memory array as mentioned in this paper.
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NAND flash memory controller exporting a NAND interface
TL;DR: A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory devices) fabricated on a flash die is disclosed in this paper.
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